32-BIT ARM-BASED MICROPROCESSORS SAM9G20 Description The SAM9G20 embedded microprocessor unit is based on the integration of an Arm926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a dual port USB Host controller with on-chip USB transceivers. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchro- nous Serial Controller, ADC and MultiMedia Card Interface. The SAM9G20 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The SAM9G20 is an enhancement of the SAM9260 with the same peripheral features. It is pin-to-pin compatible with the exception of power supply pins. Speed is increased to reach 400 MHz on the Arm core and 133 MHz on the system bus and EBI. Features Incorporates the Arm926EJ-S Arm Thumb Processor - DSP Instruction Extensions, Arm Jazelle Technology for Java Acceleration - 32-Kbyte Data Cache, 32-Kbyte Instruction Cache, Write Buffer - CPU Frequency 400 MHz - Memory Management Unit - EmbeddedICE, Debug Communication Channel Support Additional Embedded Memories - One 64-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed - Two 16-Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed External Bus Interface (EBI) - Supports SDRAM, Static Memory, ECC-enabled SLC NAND Flash and CompactFlash USB 2.0 Full Speed (12 Mbit/s) Device Port - On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM USB 2.0 Full Speed (12 Mbit/s) Host and Dual Port - Single or Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10/100 Base T - Media Independent Interface or Reduced Media Independent Interface - 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format Bus Matrix - Six 32-bit-layer Matrix - Boot Mode Select Option, Remap Command Fully-featured System Controller, including - Reset Controller, Shutdown Controller - 128-bit (4 x 32-bit) General Purpose Backup Registers - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit 2017 Microchip Technology Inc. DS60001516A-page 1SAM9G20 - Periodic Interval Timer, Watchdog Timer and Real-time Timer Reset Controller (RSTC) - Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control Clock Generator (CKGR) - Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Per- manent Slow Clock - 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention - Mode for General Purpose 2-wire UART Serial Communication Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler One 4-channel 10-bit Analog-to-Digital Converter Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output - All I/O Lines are Schmitt Trigger Inputs Peripheral DMA Controller Channels (PDC) One Two-slot MultiMedia Card Interface (MCI) - SDCard/SDIO and MultiMediaCard Compliant - Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controller (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support - Full Modem Signal Control on USART0 Two 2-wire UARTs Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Synchronous Communications Two Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability - High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 One Two-wire Interface (TWI) - Compatible with Standard Two-wire Serial Memories - One, Two or Three Bytes for Slave Address - Sequential Read/Write Operations - Master, Multi-master and Slave Mode Operation - Bit Rate: Up to 400 Kbit/s - General Call Supported in Slave Mode DS60001516A-page 2 2017 Microchip Technology Inc.