QorIQ Communications Platforms QorIQ P1010 and P1014 Communications Processors QorIQ P1010 and P1014 Block Diagram Target Markets and Applications QorIQ P1010 and P1014 Processor Block Diagram Wireless LAN access points Power Architecture (802.11ac/802.11n) e500-v2 Core 256 KB 16/32-bit DDR3/3L SOHO/SMB routers 32 KB 32 KB Frontside Memory Controller D Cache I Cache Cache (16-bit only for the P1014) Controller for Ethernet switches Security Fuse Network attached storage Processor Coherent System Bus Security Monitor Video surveillance 2x FlexCAN Factory automation and industrial control Security USB 2.0 w/PHY DMA 4.4 IFC, TDM 1 GE 1 GE 1 GE SATA SATA SD/MMC (P1010 only) 2x DUART PCIe PCIe 2 2x I C SPI, GPIO 6-Lane 2.5 GHz SerDes (P1010 only) Core Complex (CPU and L2 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements Overview Secure Boot The secure boot feature ensures that the The QorIQ P1010 and P1014 processors are processors only run authenticated code. members of the value-perfomance tier, offering Through a set of fuses that OEMs can extensive integration and extreme power program once but can never be read, secure intelligence for a wide variety of applications in cost-sensitive networking, network boot prevents unauthorized parties from attached storage, digital video surveillance reverse engineering code to steal intellectual and industrial segments. Based on 45 nm property, from loading illegitimate code to technology for low-power implementation, change system functionality or from extracting the P1010 and P1014 processors provide a sensitive user information that may be stored single-core, low-power solution for the 533 in the system. to 1000 MHz performance range, along with a trusted security platform and a rich set of interfaces. High-speed interfaces (not all available Security Engine Dual FlexCAN controllers simultaneously) The QorIQ security engine (SEC) is optimized Two FlexCAN (revision 2.0B) controllers provide Six SerDes to 3.125 GHz multiplexed to handle all the algorithms associated with a standard interface for implementing industrial across controllers IPSec, IEEE Std. 802.11i standard, and iSCSI. protocols. Each FlexCAN controller has the Two PCI Express controllers The security engine also supports booting to a following features: Two SGMII interfaces known good state, untamperable boot code, Programmable bit rates up to 1 Mb/s Two SATA interfaces key storage, I/O protection, and secure debug. Standard data and remote frames One USB controller (USB 2.0) with The SEC is a modular and scalable security Extended data and remote frames integrated PHY, host, OTG and device core optimized to process all the algorithms support Up to eight bytes data length associated with IPsec, IKE, SSL/TLS, Serial peripheral interface Up to 64 message buffers (MB), each iSCSI, SRTP, IEEE Std. 802.11i , IEEE Std. Trusted boot platform, integrated security configurable as Rx or Tx 802.16 (WiMAX), and IEEE Std. 802.1AE engine (SEC 4.0) Individual Rx mask registers per message (MACSec). The SEC is designed to perform Crypto algorithm support includes buffers multi-algorithmic operations (for example, 3DES, AES, RSA/ECC, MD5/ 3DES-HMAC-SHA-1) in a single pass of the Rx FIFO with storage capacity of six frames SHA, ARC4, Snow 3G and FIPS data. The security coprocessor in the QorIQ and internal pointer handling deterministic RNG P1010 processor is capable of performing Rx FIFO ID filtering Single pass encryption/message single-pass security cryptographic processing Time stamp based on 16-bit free running authentication for common security for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, protocols (IPsec, SSL, SRTP, WiMAX) timer and IEEE Std. 802.11i. XOR acceleration Technical Specifications SEC Features 16/32-bit DDR3/DDR3L SDRAM memory Single e500 core, built on Power controller with ECC support XOR engine for parity checking in RAID Architecture technology Four-channel DMA controller storage applications 36-bit physical addressing 2 Two I C controllers, two DUARTs, timers Four crypto-channels, each supporting Double-precision floating-point support Integrated flash controller with enhanced multi-command descriptor chains 32 KB L1 instruction cache and 32 KB capabilities to support large pages L1 data cache Cryptographic Execution Units: 32 general-purpose I/O signals 533 MHz to 800 MHz core clock PKHA (public key hardware accelerator) Package: 425-pin TEPBGA1, 0.8 mm pitch, frequency DESA (DES accelerator) 19 mm x 19 mm 256 KB L2 cache with ECC, also AESA (AES accelerator) configurable as SRAM and stashing Software and Tools Support MDHA (message digest hardware memory Enea : Real-time operating system support accelerator) Three 10/100/1000 Mb/s enhanced three- Green Hills : Complete portfolio of RNG (random number generator) speed Ethernet controllers (eTSECs) software and hardware development tools, TCP/IP acceleration and classification AFHA (ARC four hardware accelerator) trace tools and real-time operating systems capabilities STHA (SNOW 3G f8 and f9 hardware Mentor Graphics : Commercial grade Linux IEEE 1588 support accelerators) solution Lossless flow control CRCA (cyclic redundancy check P1010 reference design board (RDB) RGMII, SGMII accelerator) KFHA (Kasumi hardware accelerator) QorIQ P1010 and P1014 Comparison QorIQ Device Top Core Frequency L2 Size DDR 3 Support GE Ports SATA PCI Express Security CAN P1010 1000 MHz 256 KB 16/32-bit 800 MHz 3 2 2 Trusted 2 P1014 800 MHz 256 KB 16-bit 800 MHz 2 2 2 No No For more information about QorIQ products, visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2010, 2013 Freescale Semiconductor, Inc. Document Number: QP1010FS REV 1