Features Core ARM926EJ-S ARM Thumb Processor running up to 400 MHz 1.0V +/- 10% 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories One 128-Kbyte internal ROM embedding bootstrap routine One 32-Kbyte internal SRAM, single-cycle access at system speed 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC) AT91SAM System running up to 133 MHz Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, ARM-based Watchdog Timer and Real Time Clock Boot Mode Select Option, Remap Command Embedded MPU Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized for USB Six 32-bit-layer AHB Bus Matrix SAM9N12 Dual Peripheral Bridge with dedicated programmable clock One dual port 8-channel DMA Controller Advanced Interrupt Controller and Debug Unit Two Programmable External Clock Signals Low Power Mode Shut Down Controller with four 32-bit battery backup registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Summary Capabilities Peripherals LCD Controller USB Device Full Speed with dedicated On-Chip Transceiver USB Host Full Speed with dedicated On-Chip Transceiver One High speed SD card and SDIO Host Controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 32-bit Timer/Counters One Synchronous Serial Controller One Four-channel 16-bit PWM Controller Two Two-wire Interfaces Four USARTs plus two UARTs One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support Customizing TRNG True Random Number Generator compliant with NIST Special Publication 800-22 320 Fuse bits for device configuration, including JTAG disable and forced boot from the on-chip ROM I/O Four 32-bit Parallel Input/Output Controllers 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output Package: 217-ball BGA, pitch 0.8 mm 11096ASATARM4-Oct-111. Description The ARM926EJ-S based SAM9N12 features the frequently requested combination of user inter- face functionality and high data rate connectivity, including LCD Controller, resistive touch- screen, multiple UARTs, SPI, I2C, full speed USB Host and Device and SDIO. The SAM9N12 supports the latest generation of LPDDR/DDR2 and NAND Flash memory inter- faces for program and data storage. An internal 125 MHz multi-layer bus architecture associated with 8 DMA channels, a distributed memory including a 32-Kbyte SRAM, sustains the high band- width required by the processor and the high speed peripherals. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing. The SAM9N12 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. 2 SAM9N12 11096ASATARM4-Oct-11