Features Low-voltage and Standard-voltage Operation 2.7 (V = 2.7V to 5.5V) CC 1.8 (V = 1.8V to 5.5V) CC User Selectable Internal Organization 16K: 2048 x 8 or 1024 x 16 Three-wire Serial Interface Sequential Read Operation Schmitt Trigger, Filtered Inputs for Noise Suppression 2 MHz Clock Rate (5V) Compatibility Self-timed Write Cycle (10 ms max) Three-wire High Reliability Endurance: 1 Million Write Cycles Serial Data Retention: 100 Years Automotive Devices Available EEPROM 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8- lead TSSOP Packages 16K (2048 x 8 or 1024 x 16) Die Sales: Wafer Form, Waffle Pack and Bumped Wafers Description AT93C86A The AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin is connected to V and 2048 words of eight bits each when it is tied to ground. The CC device is optimized for use in many industrial and commercial applications where low- power and low-voltage operations are essential. The AT93C86A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8- lead TSSOP packages. Table 1. Pin Configurations 8-lead PDIP Pin Name Function CS 1 8 VCC CS Chip Select SK 2 7 NC DI 3 6 ORG SK Serial Data Clock DO 4 5 GND DI Serial Data Input DO Serial Data Output 8-lead SOIC GND Ground CS 1 8 VCC VCC Power Supply SK 2 7 NC DI 3 6 ORG ORG Internal Organization DO 4 5 GND NC No Connect 8-lead 8-lead TSSOP Ultra Thin Mini-MAP (MLP CS 1 8 VCC 2x3) SK 2 7 NC DI 3 6 ORG VCC 8 1 CS DO 4 5 GND NC 7 2 SK 3 ORG 6 DI 5 4 GND DO Bottom View Rev. 3408HSEEPR1/07 1The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The Write cycle is completely self-timed and no separate Erase cycle is required before Write. The Write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C86A is available in a 2.7V to 5.5V version. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under Absolute Operating Temperature......................................55C to +125C Maximum Ratings may cause permanent dam- Storage Temperature .........................................65C to +150C age to the device. This is a stress rating only and functional operation of the device at these or any Voltage on any Pin other conditions beyond those indicated in the with Respect to Ground ........................................ 1.0V to +7.0V operational sections of this specification is not implied. Exposure to absolute maximum rating Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect device reliability DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram Vcc GND MEMORY ARRAY ADDRESS 2048 x 8 ORG DECODER OR 1024 x 16 DATA REGISTER OUTPUT DI BUFFER MODE DECODE CS LOGIC CLOCK DO SK GENERATOR Note: When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. 2 AT93C86A 3408HSEEPR1/07