Features High-density, High-performance Electrically-erasable Complex Programmable Logic Device 44-pin, 32 I/O CPLD 7.5 ns Maximum Pin-to-pin Delay Registered Operation Up to 125 MHz Fully Connected Input and Feedback Logic Array Backward Compatibility with ATF1500/L Software and Hardware Flexible Logic Macrocell D/T/Latch Configurable Flip-flops Global and Individual Register Control Signals High- Global and Individual Output Enable Programmable Output Slew Rate performance Advanced Power Management Features Automatic 3 mA Standby (ATF1500AL) EPLD Pin-controlled 10 mA Standby Mode Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in 44-lead PLCC and TQFP Packages ATF1500A Advanced Flash Technology 100% Tested Completely Reprogrammable ATF1500AL 100 Program/Erase Cycles 20 Year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity Supported by Popular third-arty Tools Security Fuse Feature Pin-compatible with the Most Commonly Used Devices Green (Pb/Halide-fee/RoHS Compliant) Package Options Description The ATF1500A is a high-performance, high-density complex PLD. Built on an advanced Flash technology, it has maximum pin-to-pin delays of 7.5 ns and supports sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs. The ATF1500As global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes. (continued) Pin Configurations Pin PLCC TQFP Name Function Top View Top View CLK Clock I Logic Inputs Bi-directional I/O 7 39 I/O I/O I/O 1 33 I/O I/O 8 38 I/O Buffers I/O 2 32 I/O I/O 9 37 I/O I/O 3 31 I/O GND 10 36 I/O GND 4 30 I/O Register Reset I/O 11 35 VCC I/O 5 29 VCC GCLR I/O 12 34 I/O (active low) I/O 6 28 I/O I/O 13 33 I/O I/O 7 27 I/O I/O 14 32 I/O I/O 8 26 I/O OE1, Output Enable VCC 15 31 I/O VCC 9 25 I/O I/O 16 30 GND OE2 (active low) I/O 10 24 GND I/O 17 29 I/O I/O 11 23 I/O VCC +5V Supply Rev. 0759F6/05 Power-down PD (active high) 1 I/O 18 6 I/O I/O 19 5 I/O I/O 20 4 I/O/PD I/O 21 3 VCC GND 22 2 OE2/I VCC 23 1 GCLR/I I/O 24 44 OE1/I I/O 25 43 CLK/I I/O 26 42 GND I/O 27 41 I/O I/O 28 40 I/O I/O 12 44 I/O I/O 13 43 I/O I/O 14 42 I/O/PD I/O 15 41 VCC GND 16 40 OE2/I VCC 17 39 GCLR/I I/O 18 38 OE1/I I/O 19 37 CLK/I I/O 20 36 GND I/O 21 35 I/O I/O 22 34 I/O(1) Functional Logic Diagram Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow. The ATF1500A has 32 bi-directional I/O pins and four dedi- Each of the 32 logic macrocells generates a buried feed- cated input pins. Each dedicated input pin can also serve back, which goes to the global bus. Each input and I/O pin as a global control signal: register clock, register reset or also feeds into the global bus. Because of this global bus- output enable. Each of these control signals can be ing, each of these signals is always available to all 32 mac- selected for use individually within each macrocell. rocells in the device. 2 ATF1500A(L)