ATF1502AS and ATF1502ASL High-performance EEPROM Complex Programmable Logic Device DATASHEET Features High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 32 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44 Pins 7.5ns Maximum Pin-to-pin Delay Registered Operation up to 125MHz Enhanced Routing Resources In-System Programmability (ISP) via JTAG Flexible Logic Macrocell D/T Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register with a COM Output Advanced Power Management Features Automatic 10 A Standby for L Version Pin-controlled 1mA Standby Mode Programmable Pin-keeper Inputs and I/Os Reduced-power Feature per Macrocell Available in Commercial and Industrial Temperature Ranges Available in 44-lead PLCC and 44-lead TQFP Advanced EEPROM Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20 Year Data Retention 2000V ESD Protection 200mA Latch-up Immunity JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported PCI-compliant Security Fuse Feature Green (Pb/Halide-fee/RoHS Compliant) Package Options Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet 032014Enhanced Features Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms D Latch Mode Combinatorial Output with Registered Feedback within Any Macrocell Three Global Clock Pins ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (L Versions) Fast Registered Input from Product Term Programmable Pin-keeper Option V Power-up Reset Option CC Pull-up Option on JTAG Pins TMS and TDI Advanced Power Management Features Input Transition Detection Power-down (L Versions) Individual Macrocell Power Option Disable ITD on Global Clocks, Inputs, and I/O Description The Atmel ATF1502AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the Atmel proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1502AS(L)s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502AS(L) has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can serve as a global control signal, register clock, register reset, or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 32 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS(L) allows fast, efficient generation of complex logic functions. The ATF1502AS(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1502AS(L) macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: Product Terms and Product Term Select Multiplexer OR/XOR/CASCADE Logic Flip-flop Output Select and Enable Logic Array Inputs 2 ATF1502AS(L) DATASHEET Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet 032014