Features High-density, High-performance, Electrically-erasable Complex Programmable Logic Device 3.0 to 3.6V Operating Range 32 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 44 Pins 15 ns Maximum Pin-to-pin Delay Registered Operation up to 77 MHz High- Enhanced Routing Resources In-System Programmability (ISP) via JTAG performance Flexible Logic Macrocell D/T Latch Configurable Flip-flops EEPROM CPLD Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option ATF1502ASV Maximum Logic Utilization by Burying a Register with a COM Output Advanced Power Management Features Pin-controlled 0.75 mA Standby Mode Programmable Pin-keeper Inputs and I/Os Reduced-power Feature per Macrocell Available in Commercial and Industrial Temperature Ranges Available in 44-lead PLCC and TQFP Advanced EEPROM Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported PCI-compliant Security Fuse Feature Green (Pb/Halide-fee/RoHS Compliant) Package Options Enhanced Features Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms D Latch Mode Combinatorial Output with Registered Feedback within Any Macrocell Three Global Clock Pins Fast Registered Input from Product Term Programmable Pin-keeper Option V Power-up Reset Option CC Pull-up Option on JTAG Pins TMS and TDI Advanced Power Management Features Individual Macrocell Power Option 1615JPLD01/061. Description The ATF1502ASV is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmels proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502ASVs enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502ASV has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Figure 1-1. 44-lead TQFP Top View I/O/TDI 1 33 I/O I/O 2 32 I/O/TDO I/O 3 31 I/O GND 4 30 I/O PD1/I/O 5 29 VCC I/O 6 28 I/O TMS/I/O 7 27 I/O I/O 8 26 I/O/TCK VCC 9 25 I/O I/O 10 24 GND I/O 11 23 I/O Figure 1-2. 44-lead PLCC Top View TDI/I/O 7 39 I/O I/O 8 38 I/O/TDO I/O 9 37 I/O GND 10 36 I/O PD1/I/O 11 35 VCC I/O 12 34 I/O I/O/TMS 13 33 I/O I/O 14 32 I/O/TCK VCC 15 31 I/O I/O 16 30 GND I/O 17 29 I/O 2 ATF1502ASV 1615JPLD01/06 I/O 18 6 I/O I/O 12 44 I/O I/O 19 5 I/O I/O 13 43 I/O I/O 20 4 I/O I/O 14 42 I/O I/O 21 3 VCC I/O 15 41 VCC GND 22 2 GCLK2/OE2/I GND 16 40 GCLK2/OE2/I VCC 17 39 GCLR/I VCC 23 1 GCLR/I I/O 18 38 I/OE1 I/O 24 44 OE1/I PD2/I/O 19 37 GCLK1/I PD2/I/O 25 43 GCLK1/I I/O 20 36 GND I/O 26 42 GND I/O 21 35 GCLK3/I/O 41 I/O 27 GCLK3/I/O I/O 22 34 I/O I/O 28 40 I/O