ATF1504ASV/ATF1504ASVL ATF1504ASV(L) 3.3V 64-Macrocell CPLD Data Sheet Features Enhanced Features High-Density, High-Performance, Electri- Improved Connectivity (Additional Feedback cally-Erasable Complex Programmable Logic Routing, Alternate Input Routing) Device: Output Enable Product Terms - 3.0V to 3.6V operating range Transparent-Latch Mode - 64 macrocells Combinatorial Output with Registered Feedback - 5 product terms per macrocell, expandable within any Macrocell up to 40 per macrocell Three Global Clock Pins - 44 and 100 pins ITD (Input Transition Detection) Circuits on Global - 15 ns maximum pin-to-pin delay Clocks, Inputs and I/O - Registered operation up to 77 MHz Fast Registered Input from Product Term - Enhanced routing resources Programmable Pin-keeper Option CC Power-Up Reset Option In-System Programmability (ISP) via JTAG V Flexible Logic Macrocell: Pull-Up Option on JTAG Pins (TMS and TDI) - D/T/Latch configurable flip-flops Advanced Power Management Features: - Global and individual register control signals - Edge-controlled power-down (ATF1504ASVL) - Global and individual output enable - Individual macrocell power option - Programmable output slew rate - Disable ITD on global clocks - Programmable output open-collector option - Maximum logic utilization by burying a regis- Packages ter with a COM output Advanced Power Management Features: 44-Lead PLCC - Automatic 5 A Standby (ATF1504ASVL) 44-Lead and 100-Lead TQFP - Pin-controlled 100 A Standby mode (typical) - Programmable pin-keeper circuits on inputs Description and I/Os The ATF1504ASV(L) is a high-performance, high-den- - Reduced-power feature per macrocell sity complex programmable logic device (CPLD) that Available in Industrial Temperature Range utilizes Microchips proven electrically-erasable mem- Robust EEPROM Technology: ory technology. With 64 logic macrocells and up to - 100% tested 68 inputs and I/Os, it easily integrates logic from sev- eral TTL, SSI, MSI, LSI and classic PLDs. The - Completely reprogrammable ATF1504ASV(L)s enhanced routing switch matrices - 10,000 Program/Erase cycles increase usable gate count and the odds of successful - 20-year data retention pin-locked design modifications. - 2000V ESD protection The ATF1504ASV(L) has up to 64 bidirectional I/O pins - 200 mA latch-up immunity and four dedicated input pins, depending on the type of JTAG Boundary-Scan Testing to IEEE Std. device package selected. Each dedicated pin can also 1149.1-1990 and 1149.1a-1993 Supported serve as a global control signal (register clock, register PCI-Compliant Reset or output enable). Each of these control signals can be selected for use individually within each Security Fuse Feature macrocell. Green (Pb/Halide-Free/RoHS Compliant) Package Options 2019 Microchip Technology Inc. DS20006185A-page 1ATF1504ASV/ATF1504ASVL Each of the 64 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1504- ASV(L) allows fast, efficient generation of complex logic functions. The ATF1504ASV(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504ASV(L) macrocell (see ATF1504ASV(L) Macrocell), is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. ATF1504ASV(L) Macrocell 2019 Microchip Technology Inc. DS20006185A-page 2