Features 3.0V to 5.5V Operation Industry-standard Architecture Emulates Many 20-pin PALs Low-cost Easy-to-use Software Tools High-speed 10 ns Maximum Pin-to-pin Delay Ultra-low Power 5 A (Max) Pin-controlled Power-down Mode Option Typical 100 nA Standby CMOS and TTL Compatible Inputs and Outputs High- I/O Pin-keeper Circuits Advanced Flash Technology performance Reprogrammable 100% Tested EE PLD High-reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection ATF16LV8C 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts Inputs are 5V Tolerant Green Package Options (Pb/Halide-free/RoHS Compliant) Available Description The ATF16LV8C is a high-performance EECMOS programmable logic device that uti- lizes Atmels proven electrically-erasable Flash memory technology. Speeds down to 10 ns and a 5 A pin-controlled power-down mode option are offered. All speed (continued) Pin Configurations TSSOP All Pinouts Top View I/CLK 1 20 VCC Pin Name Function I1 2 19 I/O I2 3 18 I/O CLK Clock PD/I3 4 17 I/O I4 5 16 I/O I Logic Inputs I5 6 15 I/O I6 7 14 I/O I/O Bi-directional Buffers I7 8 13 I/O OE Output Enable I8 9 12 I/O GND 10 11 I9/OE VCC (+3V to 5.5V) Supply Programmable Power- PD down Option DIP/SOIC PLCC I/CLK 1 20 VCC I1 2 19 I/O I2 3 18 I/O PD/I3 4 17 I/O I4 5 16 I/O PD/I3 4 18 I/O I5 6 15 I/O I4 5 17 I/O I6 7 14 I/O I5 6 16 I/O I7 8 13 I/O I6 7 15 I/O I8 9 12 I/O I7 8 14 I/O Rev. 0403H06/06 GND 10 11 I9/OE 1 I8 9 3 I2 GND 10 2 I1 I9/OE 11 1 I/CLK I/O 12 20 VCC I/O 13 19 I/Oranges are specified over the full 3.0V to 5.25V range for The ATF16LV8C can significantly reduce total system industrial and commercial temperature ranges. power, thereby enhancing system reliability and reducing power supply costs. When pin 4 is configured as the The ATF16LV8C incorporates a superset of the generic power-down control pin, supply current drops to less than architectures, which allows direct replacement of the 16R8 5 A whenever the pin is high. If the power-down feature family and most 20-pin combinatorial PLDs. Eight outputs isn t required for a particular application, pin 4 may be used are each allocated eight product terms. Three different as a logic input. Also, the pin keeper circuits eliminate the modes of operation, configured automatically with soft- need for internal pull-up resistors along with their attendant ware, allow highly complex logic functions to be realized. power consumption. Block Diagram Note: 1. Includes optional PD control pin. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under Absolute Temperature Under Bias.................................. -40C to +85C Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ..................................... -65C to +150C functional operation of the device at these or any Voltage on Any Pin with other conditions beyond those indicated in the (1) Respect to Ground .........................................-2.0V to +7.0V operational sections of this specification is not implied. Exposure to absolute maximum rating Voltage on Input Pins conditions for extended periods may affect device with Respect to Ground reliability. (1) During Programming.....................................-2.0V to +14.0V Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V DC, Programming Voltage with (1) which may overshoot to 7.0V for pulses of less Respect to Ground .......................................-2.0V to +14.0V than 20 ns. DC and AC Operating Conditions Commercial Operating Temperature (Ambient) 0C - 70C V Power Supply 3.0V to 5.5V CC 2 ATF16LV8C