Features High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells 48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops ATF2500C Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback CPLD Family Backward Compatible with ATV2500B/BQ and ATV2500H Software Advanced Electrically-erasable Technology Datasheet Reprogrammable 100% Tested 44-lead Surface Mount Package and 40-pin DIP Package Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs ATF2500C Simultaneously 8 Synchronous Product Terms Individual Asynchronous Reset per Macrocell OE Control per Macrocell Functionality Equivalent to ATV2500B/BQ and ATV2500H 2000V ESD Protection Security Fuse Feature to Protect the Code Commercial, Industrial and Military Temperature Range Offered 10 Year Data Retention Pin Keeper Option 200 mA Latch-up Immunity Green Package Options (Pb/Halide-free/RoHS Compliant) Available 1. Description The ATF2500C is the highest-density PLD available in a 44-pin surface mount pack- age. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electri- cally-erasable) programmable logic device (PLD) that utilizes Atmels proven electrically-erasable technology. This PLD is now available in a fully Green or LHF (lead and halide-free) packages. Figure 1-1. Block Diagram 0777KPLD1/24/08The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out- puts of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocells three sum terms can be combined to provide up to 12 product terms per sum term with no per- formance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combina- torial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automati- cally reset upon power-up. 2. Pin Configurations Table 2-1. Pin Configurations Pin Name Function IN Logic Inputs CLK/IN Pin Clock and Input I/O Bi-directional Buffers I/O 0,2,4... Even I/O Buffers I/O 1,3,5... Odd I/O Buffers GND Ground VCC +5V Supply Figure 2-1. DIP Figure 2-2. PLCC CLK/IN 1 40 IN IN 2 39 IN IN 3 38 IN I/O2 7 39 I/O7 I/O0 4 37 IN I/O3 8 38 I/O8 I/O1 5 36 I/O6 I/O4 9 37 I/O9 I/O2 6 35 I/O7 I/O5 10 36 I/O10 I/O3 7 34 I/O8 VCC 11 35 I/O11 I/O4 8 33 I/O9 VCC 12 34 GND I/O5 9 32 I/O10 I/O17 13 33 GND VCC 10 31 I/O11 I/O16 14 32 I/O23 I/O17 11 30 GND I/O15 15 31 I/O22 I/O16 12 29 I/O23 I/O14 16 30 I/O21 I/O15 13 28 I/O22 I/O13 17 29 I/O20 I/O14 14 27 I/O21 I/O13 15 26 I/O20 I/O12 16 25 I/O19 IN 17 24 I/O18 IN 18 23 IN IN 19 22 IN IN 20 21 IN Note: (PLCC package) pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity. 2 ATF2500C 0777KPLD1/24/08 6 I/O12 18 I/O1 IN 19 5 I/O0 IN 20 4 GND IN 21 3 IN IN 22 2 IN IN 23 1 CLK/IN IN 24 44 IN IN 25 43 IN GND 26 42 IN I/O18 27 41 IN I/O19 28 40 I/O6