Features High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories 16/32/64K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles 8-bit Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program Microcontroller True Read-While-Write Operation 512B/1K/2K Bytes EEPROM with 16/32/64K Endurance: 100,000 Write/Erase Cycles 1/2/4K Bytes Internal SRAM Bytes In-System Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Programmable Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Flash Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode ATmega164P Real Time Counter with Separate Oscillator Six PWM Channels ATmega324P 8-channel, 10-bit ADC (1) Differential mode with selectable gain at 1x, 10x or 200x ATmega644P Byte-oriented Two-wire Serial Interface Two Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator Automotive On-chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages 32 Programmable I/O Lines 44-lead TQFP, and 44-pad QFN/MLF Operating Voltages 2.7 - 5.5V for ATmega164P/324P/644P Speed Grades ATmega164P/324P/644P: 0 - 8MHz 2.7 - 5.5V, 0 - 16MHz 4.5 - 5.5V Power Consumption at 8 MHz, 5V, 25C for ATmega644P Active mode: 8 mA Idle mode: 2.4 mA Power-down Mode: 0.8 A 7674FAVR09/091. Pin Configurations Figure 1-1. Pinout ATmega164P/324P/644P TQFP/QFN/MLF (PCINT13/MOSI) PB5 PA4 (ADC4/PCINT4) (PCINT14/MISO) PB6 PA5 (ADC5/PCINT5) (PCINT15/SCK) PB7 PA6 (ADC6/PCINT6) RESET PA7 (ADC7/PCINT7) VCC AREF GND GND XTAL2 AVCC XTAL1 PC7 (TOSC2/PCINT23) (PCINT24/RXD0) PD0 PC6 (TOSC1/PCINT22) (PCINT25/TXD0) PD1 PC5 (TDI/PCINT21) (PCINT/RXD1/26/INT0) PD2 PC4 (TDO/PCINT20) Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 2 ATmega164P/324P/644P 7674FAVR09/09 PB4 (SS/OC0B/PCINT12) (PCINT/TXD1/27/INT1) PD3 PB3 (AIN1/OC0A/PCINT11) (PCINT28/XCK1/OC1B) PD4 PB2 (AIN0/INT2/PCINT10) (PCINT29/OC1A) PD5 PB1 (T1/CLKO/PCINT9) (PCINT30/OC2B/ICP) PD6 PB0 (XCK0/T0/PCINT8) (PCINT31/OC2A) PD7 GND VCC VCC GND PA0 (ADC0/PCINT0) (PCINT16/SCL) PC0 PA1 (ADC1/PCINT1) (PCINT17/SDA) PC1 PA2 (ADC2/PCINT2) (PCINT18/TCK) PC2 PA3 (ADC3/PCINT3) (PCINT19/TMS) PC3