SAMA5D2 Series
Ultra-Low-Power Arm Cortex-A5 Core-Based MPU,
500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB,
PCI 5.0 Pre-Certified
Introduction
The SAMA5D2 series is a high-performance, ultra-low-power Arm Cortex-A5 CPU-based embedded
microprocessor (MPU) running up to 500 MHz, with support for multiple memories such as DDR2,
DDR3L, LPDDR2, LPDDR3, and QSPI and e.MMC Flash. The devices integrate powerful peripherals for
connectivity and user interface applications, and offer advanced security functions (Arm TrustZone ,
tamper detection, secure data storage, etc.), as well as high-performance crypto accelerators AES, SHA
and TRNG.
Selected members of the SAMA5D2 series are qualified for extended industrial temperature range
operation (-40C to 105C external temperature).
The SAMA5D2 series is delivered with a free Linux distribution and bare metal C examples.
Features
Arm Cortex-A5 Core
Armv7-A architecture
Arm TrustZone
NEON Media Processing Engine
Up to 500 MHz
ETM/ETB 8 Kbytes
Memory Architecture
Memory Management Unit (MMU)
32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
128-Kbyte L2 cache configurable to be used as an internal SRAM
One 128-Kbyte scrambled internal SRAM
One 160-Kbyte internal ROM
64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader
96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM
controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off
only) / LPDDR1/LPDDR2/LPDDR3, including on-the-fly encryption/decryption path
8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
System Running up to 166 MHz in Typical Conditions
Datasheet Complete DS60001476C-page 1
2018 Microchip Technology Inc. SAMA5D2 Series
Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT),
independent Watchdog Timer (WDT) and secure Real-Time Clock (RTC) with clock calibration
One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for high-speed USB
Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
Internal low-power 12 MHz RC and 32 kHz typical RC
Selectable 32.768 Hz low-power oscillator and 8 to 24 MHz oscillator
51 DMA channels including two 16-channel 64-bit Central DMA Controllers
64-bit Advanced Interrupt Controller (AIC)
64-bit Secure Advanced Interrupt Controller (SAIC)
Three programmable external clock signals
Low-Power Modes
Ultra-low-power mode with fast wake-up capability
Low-power Backup mode with 5-Kbyte SRAM and SleepWalking features
Wake up from up to nine wake-up pins, UART reception, analog comparison
Fast wake-up capability
Extended Backup mode with DDR in Self-Refresh mode
Peripherals
LCD TFT controller (LCDC) up to 1024x768 or 1280x768 (still image). Four overlays, rotation,
post-processing and alpha blending, 24-bit parallel RGB interface
ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 Mpixel sensors with a
parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor
interface
Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one
Stereo Class D amplifier (CLASSD)
One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive
touch)
One Pulse Density Modulation Interface Controller (PDMIC)
One USB device high-speed port (UDPHS) and one USB host high-speed port or two USB host
high-speed ports (UHPHS)
One USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface
One 10/100 Ethernet MAC (GMAC)
Energy efficiency support (IEEE 802.3az standard)
Ethernet AVB support with IEEE802.1AS timestamping
IEEE802.1Qav credit-based traffic-shaping hardware support
IEEE1588 Precision Time Protocol (PTP)
Two high-speed memory card hosts:
SDMMC0: SD 3.0, eMMC 4.51, 8 bits
SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
Two master/slave Serial Peripheral Interfaces (SPI)
Two Quad Serial Peripheral Interfaces (QSPI)
Five FLEXCOMs (USART, SPI and TWI)
Five UARTs
Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-
triggered transmission
DS60001476C-page 2
Datasheet Complete
2018 Microchip Technology Inc.