SAMA5D3 Series Low-Power Arm Cortex -A5 Processor-Based MPU, 536 MHz, FPU, Gigabit Ethernet with IEEE 1588 plus 10/100 Ethernet, Dual CAN, AES, SHA Description The Microchip SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the Arm Cortex - A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device fea- tures a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/ LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composi- tion, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE 1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of con- nectivity in the industrial and consumer markets. Its low-power consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are five SAMA5D3 devices in this series. The table SAMA5D3 Device Differences on page 3 shows the differ- ences in the embedded features. All other features are available on all derivatives this includes the three USB ports as well as the encryption engine and secure boot features. 2020 Microchip Technology Inc. DS60001609B-page 1SAMA5D3 SERIES Features Core - Arm Cortex-A5 Processor with ARMv7-A Thumb-2 Instruction Set - CPU Frequency up to 536 MHz - 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) - Fully Integrated MMU and Floating Point Unit (VFPv4) Memories - One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit NAND Flash, SDCard, eMMC, serial DataFlash, selectable Order - One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed - High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank 32-bit or 2x16-bit SDRAM devices - Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correction Code (PMECC) System running up to 166 MHz - Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock - Boot Mode Select Option, Remap Command - Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator - Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator - One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed - 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers - 64-bit Advanced Interrupt Controller - Three Programmable External Clock Signals - Programmable Fuse Box with 256 fuse bits (of which 192 are available for users) Low Power Management - Shutdown Controller - Battery Backup Registers - Clock Generator and Power Management Controller - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Peripherals - LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion - ITU-R BT. 601/656 Image Sensor Interface - Three HS/FS/LS USB Ports with On-Chip Transceivers One Device Controller One Host Controller with Integrated Root Hub (3 Downstream Ports) - One 10/100/1000 Mbps Gigabit Ethernet Media Access Controller (GMAC) with IEEE1588 support - One 10/100 Mbps Ethernet Media Access Controller (EMAC) - Two CAN Controllers with 8 Mailboxes, fully compliant with CAN 2.0 Part A and 2.0 Part B - Softmodem Interface - Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0) - Two Master/Slave Serial Peripheral Interfaces - Two Synchronous Serial Controllers - Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS - Four USARTs (ISO7816, IrDA , RS-485, SPI, Manchester and Modem Modes) -Two UARTs -One DBGU - Two 3-channel 32-bit Timer/Counters - One 4-channel 16-bit PWM Controller - One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touchscreen function Safety - Power-on Reset Cells - Independent Watchdog - Main Crystal Clock Failure Detection - Register Write Protection DS60001609B-page 2 2020 Microchip Technology Inc.