DSC2033 Low-Jitter Configurable Dual LVDS Oscillator General Description Features The DSC2033 series of high performance Low RMS Phase Jitter: <1 ps (typ) dual output LVDS oscillators utilize a proven High Stability: 10, 25, 50 ppm silicon MEMS technology to provide excellent jitter and stability while incorporating Wide Temperature Range additional device functionality. The two o Industrial: -40 to 85 C outputs are controlled by separate supply o Ext. commercial: -20 to 70 C voltages to allow for high output isolation. High Supply Noise Rejection: -50 dBc The frequencies of the outputs can be identical or independently derived from a Two Independent LVDS Outputs common PLL frequency source. The Pin-Selectable Configurations DSC2033 has provision for up to eight user- defined pre-programmed, pin-selectable o 3-bit Output Frequency Combinations output frequency combinations. Short Lead Times: 2 Weeks Wide Freq. Range: DSC2033 is packaged in a 14-pin 3.2x2.5 mm QFN package and available in o LVDS output: 2.3 460 MHz temperature grades from Ext. Commercial to Miniature Footprint of 3.2x2.5mm Industrial. Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 High Reliability o 20x better MTF than quartz oscillators Supply Range of 2.25 to 3.6 V Block Diagram Lead Free & RoHS Compliant Applications Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 10G-EPON, GPON, 10G-PON Ethernet o 1G, 10GBASE-T/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express DSC2033 Page 1 MK-Q-B-P-D-12042609-2 Low-Jitter Configurable Dual LVDS Oscillator DSC2033 Pin Description Pin No. Pin Name Pin Type Description 1 Enable I Enables outputs when high and disables when low 2 NC NA Leave unconnected or grounded 3 NC NA Leave unconnected or grounded 4 GND Power Ground 5 FS0 I Least significant bit for frequency selection 6 FS1 I Middle bit for frequency selection 7 FS2 I Most significant bit for frequency selection 8 Output1+ O Positive LVDS Output 1 9 Output1- O Negative LVDS Output 1 10 Output 2- O Negative LVDS Output 2 11 Output 2+ O Positive LVDS Output 2 12 VDD2 Power Power Supply 2 for LVDS Output 2 13 VDD Power Power Supply 14 NC NA Leave unconnected or grounded Operational Description The DSC2033 is a dual output LVDS oscillator coefficients required by the PLL for up to eight consisting of a MEMS resonator and a support different frequency combinations. Three PLL IC. The two outputs are generated control pins (FS0 FS2) select the output through independent 8-bit programmable frequency combination. Discera supports dividers from the output of the internal PLL. customer defined versions of the DSC2033. Two constraints are imposed on the output Standard frequency options are described in in frequencies: 1) f =M x f /N, where M and N the following sections. 2 1 are even integers between 4 and 254, 2) When Enable (pin 1) is floated or connected to 1.2GHz < N x f < 1.7GHz. 2 VDD, the DSC2033 is in operational mode. The actual frequencies output by the DSC2033 Driving Enable to ground will tri-state both are controlled by an internal pre-programmed output drivers (hi-impedance mode). memory (OTP). This memory stores all Output Clock Frequencies Table 1 lists the standard frequency configurations and the associated ordering information to be used in conjunction with the ordering code above. Customer defined combinations are available. Table 1. Pre-programmed pin-selectable output frequency combinations Freq Select Bits FS2, FS1, FS0 Default is 111 Ordering Freq Info (MHz) 000 001 010 011 100 101 110 111 f 148.5 156.25 150 125 125 100 100 400 OUT1 G0001 f 74.25 125 125 25 50 50 75 200 OUT2 f OUT1 100 125 0 0 0 0 0 0 G0002 f 100 125 0 0 0 0 0 0 OUT1 f OUT1 GXXXX Contact factory for additional configurations. f OUT2 Frequency select bit are weakly tied high so if left unconnected the default setting will be 1 and the device will output the associated frequency highlighted in Bold. DSC2033 Page 2 MK-Q-B-P-D-12042609-2