dsPIC33EPXXGS50X FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions Advanced Analog Features 3.0V to 3.6V, -40C to +85C, DC to 70 MIPS High-Speed ADC module: 3.0V to 3.6V, -40C to +125C, DC to 60 MIPS - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core Flash Architecture - Configurable resolution (up to 12-bit) for each ADC core Dual Partition Flash Program Memory with Live Update (64-Kbyte devices): - Up to 3.25 Msps conversion rate per channel at 12-bit resolution - Supports programming while operating - 12 to 22 single-ended inputs - Supports partition soft swap - Dedicated result buffer for each analog channel Core: 16-Bit dsPIC33E CPU - Flexible and independent ADC trigger sources Code-Efficient (C and Assembly) Architecture - Two digital comparators Two 40-Bit Wide Accumulators - Two oversampling filters for increased Single-Cycle (MAC/MPY) with Dual Data Fetch resolution Single-Cycle Mixed-Sign MUL Plus Four Rail-to-Rail Comparators with Hysteresis: Hardware Divide - Dedicated 12-bit Digital-to-Analog Converter 32-Bit Multiply Support (DAC) for each analog comparator Two Additional Working Register Sets (reduces - Up to two DAC reference outputs context switching) - Up to two external reference inputs Two Programmable Gain Amplifiers: Clock Management - Single-ended or independent ground reference 0.9% Internal Oscillator - Five selectable gains (4x, 8x, 16x, 32x and 64x) Programmable PLLs and Oscillator Clock Sources - 40 MHz gain bandwidth Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Interconnected SMPS Peripherals Fast Wake-up and Start-up Reduces CPU Interaction to Improve Performance Flexible PWM Trigger Options for Power Management ADC Conversions Low-Power Management modes (Sleep, High-Speed Comparator Truncates PWM Idle, Doze) (15 ns typical): Integrated Power-on Reset and Brown-out Reset - Supports Cycle-by-Cycle Current mode control 0.5 mA/MHz Dynamic Current (typical) - Current Reset mode (variable frequency) 10 A IPD Current (typical) Timers/Output Compare/Input Capture High-Speed PWM Five 16-Bit and up to Two 32-Bit Timers/Counters Five PWM Generators (two outputs per generator) Four Output Compare (OC) modules, Configurable Individual Time Base and Duty Cycle for each PWM as Timers/Counters 1.04 ns PWM Resolution (frequency, duty cycle, Four Input Capture (IC) modules dead time and phase) Supports Center-Aligned, Redundant, Complementary and True Independent Output modes Independent Fault and Current-Limit Inputs Output Override Control PWM Support for AC/DC, DC/DC, Inverters, PFC and Lighting 2013-2017 Microchip Technology Inc. DS70005127D-page 1dsPIC33EPXXGS50X FAMILY Communication Interfaces Qualification and Class B Support Two UART modules (15 Mbps): AEC-Q100 REVG (Grade 1, -40C to +125C) - Supports LIN/J2602 protocols and IrDA Class B Safety Library, IEC 60730 Two 4-Wire SPI modules (15 Mbps) The 6x6x0.5 mm UQFN Package is Designed and 2 Optimized to ease IPC9592B 2nd Level Two I C modules (up to 1 Mbaud) with SMBus Temperature Cycle Qualification Support Input/Output Debugger Development Support Constant-Current Source (10 A nominal) In-Circuit and In-Application Programming Sink/Source up to 12mA/15mA, respectively Five Program and Three Complex Pin-Specific for Standard VOH/VOL Data Breakpoints 5V Tolerant Pins IEEE 1149.2 Compatible (JTAG) Boundary Scan Selectable, Open-Drain Pull-ups and Pull-Downs Trace and Run-Time Watch External Interrupts on All I/O Pins Peripheral Pin Select (PPS) to allow Function Remap with Six Virtual I/Os 12-Bit Remappable Peripherals ADC Device dsPIC33EP16GS502 28 16K 2K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 SOIC, dsPIC33EP32GS502 28 32K 4K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 QFN-S, UQFN dsPIC33EP64GS502 28 64K 8K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 dsPIC33EP16GS504 44 16K 2K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 QFN, dsPIC33EP32GS504 44 32K 4K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 TQFP dsPIC33EP64GS504 44 64K 8K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dsPIC33EP16GS505 48 16K 2K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dsPIC33EP32GS505 48 32K 4K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 TQFP dsPIC33EP64GS505 48 64K 8K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 dsPIC33EP16GS506 64 16K 2K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 dsPIC33EP32GS506 64 32K 4K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 TQFP dsPIC33EP64GS506 64 64K 8K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable. 2: PWM4 and PWM5 are remappable on all devices except the 64-pin devices. 3: External interrupts, INT0 and INT4, are not remappable. DS70005127D-page 2 2013-2017 Microchip Technology Inc. Pins Program Memory Bytes RAM (Bytes) General Purpose I/O (GPIO) (1) Timers Input Capture Output Compare UART SPI (2) PWM (3) External Interrupts Reference Clock 2 I C Analog Inputs S&H Circuits PGA Analog Comparator DAC Output Constant-Current Source Packages