KSZ8775CLX Integrated 5-Port 10/100 Managed Ethernet Switch with Port 4 RMII and Port 5 RGMII/MII/ RMII Interfaces - Supports reduced media independent inter- Features face (RMII) with 50 MHz reference clock out- Management Capabilities put - The KSZ8775CLX includes all the functions - Supports media independent interface (MII) of a 10/100BASE-T/TX switch system, which in either PHY mode or MAC mode on Port 5 combines a switch engine, frame buffer - LinkMD cable diagnostic capabilities for management, address look-up table, queue determining cable opens, shorts, and length management, MIB counters, media access Advanced Switch Capabilities controllers (MAC), and PHY transceivers - Non-blocking store-and-forward switch fabric - Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing a assures fast packet delivery by utilizing a 1024-entry forwarding table 1024-entry forwarding table - 64kb frame buffer RAM - Port mirroring/monitoring/sniffing: ingress - IEEE 802.1q VLAN support for up to 128 and/or egress traffic to any port active VLAN groups (full-range 4096 of VLAN - MIB counters for fully compliant statistics IDs) gathering - 36 counters per port - IEEE 802.1p/q tag insertion or removal on a - Hardware support for port-based flush and per port basis (egress) freeze command in MIB counter. - VLAN ID tag/untag options on per port basis - Multiple loopback of remote, PHY, and MAC - Fully compliant with IEEE 802.3/802.3u stan- modes support for the diagnostics dards - Rapid spanning tree support (RSTP) for - IEEE 802.3x full-duplex with force mode topology management and ring/linear option and half-duplex back-pressure colli- recovery sion flow control Robust PHY Ports - IEEE 802.1w rapid spanning tree protocol - Four integrated IEEE 802.3/802.3u-compliant support Ethernet transceivers supporting 10Base-T - IGMP v1/v2/v3 snooping for multicast packet and 100BASE-TX filtering - 802.1az EEE supported - QoS/CoS packets prioritization support: - On-chip termination resistors and internal 802.1p, DiffServ-based and re-mapping of biasing for differential pairs to reduce power 802.1p priority field per port basis on four - HP Auto MDI/MDI-X crossover support priority levels eliminates the need to differentiate between - IPv4/IPv6 QoS support straight or crossover cables in applications - IPv6 multicast listener discovery (MLD) MAC and GMAC Ports snooping - Four internal media access control (MAC1 to - Programmable rate limiting at the ingress and MAC4) units and one internal Gigabit media egress ports on a per port basis access control (GMAC5) unit - Jitter-free per-packet-based rate limiting - RGMII, MII, or RMII interfaces support for the support Port 5 GMAC5 with uplink and RMII interface - Tail tagging mode (one byte added before for Port 4 MAC4 FCS) support on Port 5 to inform the proces- - 2 kb jumbo packet support sor which ingress port receives the packet - Tail tagging mode (one byte added before and its priority FCS) support on Port 5 to inform the - Broadcast storm protection with percentage processor which ingress port receives the control (global and per port basis) packet and its priority DS00002129D-page 1 2016-2021 Microchip Technology Inc.KSZ8775CLX - 1 kb entry forwarding table with 64 kb frame requirement buffer Comprehensive programmable two LED indicator - Four priority queues with dynamic packet support for link, activity, full/half-duplex, and 10/ mapping for IEEE 802.1p, IPv4 ToS (DIFF- 100 speed SERV), IPv6 traffic class, etc. Packaging and Environmental - Supports Wake-on-LAN (WoL) using AMDs - Commercial temperature range: 0C to Magic Packet +70C - VLAN and address filtering Industrial temperature range: 40C to +85C - Supports 802.1x port-based security, authen- - Package available in an 80-pin lead free tication, and MAC-based authentication via (RoHS) LQFP form factor access control lists (ACL) - Supports HBM ESD rating of 5 kV - Provides port-based and rule-based ACLs to - 0.065 m CMOS technology for lower power support Layer 2 MAC SA/DA address, Layer consumption 3 IP address and IP mask, Layer 4 TCP/UDP Applications port number, IP protocol, TCP flag, and com- - Set-Top Boxes pensation for the port security filtering - Networked Printers and Servers - Ingress and egress rate limit based on bit per - Test Instrumentation second (bps) and packet-based rate limiting (pps) - LAN on Motherboard Configuration Registers Access - Embedded Telecom Applications - High speed (4-wire, up to 25 MHz) interface - Video Record/Playback Systems (SPI) to access all internal registers - Cable Modems/Routers - MII management interface (MIIM, MDC/ - DSL Modems/Routers MDIO 2-wire) to access all PHY registers per - Digital Video Recorders clause 22.2.4.5 of the IEEE 802.3 specifica- - IP and Video Phones tion - Wireless Access Points - I/O pin strapping facility to set certain register - Digital Televisions bits from I/O pins during reset time - Digital Media Adapters/Servers - Control registers configurable on-the-fly - Gaming Consoles Power and Power Management - Full-chip software power down (all registers value are not saved and strap-in value will re- strap after release of the power down) - Per-port software power down - Energy detect power down (EDPD), which disables the PHY transceiver when cables are removed - Supports IEEE P802.3az Energy Efficient Ethernet to reduce power consumption in transceivers in LPI state even though cables are not removed - Dynamic clock tree control to reduce clocking in areas not in use - Low power consumption without extra power consumption on transformers - Voltages: Using external LDO power sup- plies. - Analog VDDAT 3.3V - VDDIO supports 3.3V, 2.5V, and 1.8V - Low 1.2V voltage for analog and digital core power - Wake-on-LAN support with configurable packet control Additional Features - Single 25 MHz +50 ppm reference clock 2016-2021 Microchip Technology Inc. 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