KSZ8863MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs Revision 1.5 General Description The KSZ8863MLL/FLL/RLL are highly-integrated 3-port The configurations provided by the KSZ8863 family switch on a chip ICs in industrys smallest footprint. They enables the flexibility to meet requirements of different are designed to enable a new generation of low port applications: count, cost-sensitive and power efficient 10/100Mbps KSZ8863MLL: Two 10/100BASE-T/TX transceivers switch systems. Low power consumption, advanced and one MII interface. power management, and sophisticated QoS features KSZ8863RLL: Two 10/100BASE-T/TX transceivers (e.g., IPv6 priority classification support) make these and one RMII interface. devices ideal for IPTV, IP-STB, VoIP, automotive and KSZ8863FLL: One 100BASE-FX, one 10/100BASE- industrial applications. T/TX transceivers and one MII interface. The KSZ8863 family is designed to support the GREEN requirement in todays switch systems. Advanced power management schemes include software power down, The device is available in RoHS-compliant 48-pin LQFP per port power down and the energy detect mode that package. Industrial-grade and Automotive-grade are also available. shuts downs the transceiver when a port is idle. KSZ8863MLL/FLL/RLL also offer a by-pass mode, which The datasheets and supporting documents can be found at Micrels web site at: www.micrel.com. enables system-level power saving. In this mode, the processor connected to the switch through the MII interface can be shut down without impacting the normal switch operation. Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8863MLL/FLL//RLL Features Advanced Switch Features - IEEE 802.1q VLAN support for up to 16 groups - Full duplex IEEE 802.3x flow control (PAUSE) with force mode option (full-range of VLAN IDs) - Half-duplex back pressure flow control - VLAN ID tag/untag options, per port basis - HP Auto MDI-X for reliable detection of and - IEEE 802.1p/q tag insertion or removal on a per correction for straight-through and crossover port basis (egress) cables with disable and enable option - Programmable rate limiting at the ingress and TDR-based cable diagnostics egress on a per port basis - Micre LinkMD permit identification of faulty copper cabling - Broadcast storm protection with % control - MII interface supports both MAC mode and PHY (global and per port basis) mode - IEEE 802.1d rapid spanning tree protocol - Comprehensive LED Indicator support for link, support activity, full/half duplex and 10/100 speed - tail tag mode (1 byte added before FCS) support - HBM ESD Rating 4kV at port3 to inform the processor which ingress port receives the packet and its priority Switch Monitoring Features - Bypass feature which Automatically sustains the - Port mirroring/monitoring/sniffing: ingress and/or switch function between Port1 and Port2 when egress traffic to any port or MII CPU (Port 3 interface) goes to the sleep mode - MIB counters for fully compliant statistics - Self-address filtering gathering 34 MIB counters per port - Individual MAC address for port1 and port2 - Loopback modes for remote diagnostic of failure - Support RMII interface and 50 MHz reference Low Power Dissipation clock output - Full-chip software power-down (register - IGMP snooping (Ipv4) support for multicast configuration not saved) packet Filtering - Energy-detect mode support - IPv4/IPv6 QoS support. - Dynamic clock tree shutdown feature - MAC filtering function to forward unknown - Per port based software power-save on PHY unicast packets to specified port (idle link detection, register configuration Comprehensive Configuration Register Access preserved) - Serial management interface (SMI) to all internal - Voltages: Single 3.3V supply with internal 1.8V registers LDO for 3.3V VDDIO - MII management (MIIM) interface to PHY - Optional 3.3V, 2.5V and 1.8V for VDDIO registers - Transceiver power 3.3V for VDDA 3.3 2 - High speed SPI and I C Interface to all internal o o Industrial Temperature Range: 40 C to +85 C registers Available in 48-Pin LQFP, Lead-free package - I/0 pins strapping and EEPROM to program Applications selective registers in unmanaged switch mode - Control registers configurable on the fly (port- Typical priority, 802.1p/d/q, AN) - VoIP Phone QoS/CoS Packet Prioritization Support - Set-top/Game Box - Per port, 802.1p and DiffServ-based - Automotive - Re-mapping of 802.1p priority field per port - Industrial Control basis Four priority levels - IPTV POF Proven Integrated 3-Port 10/100 Ethernet Switch - SOHO Residential Gateway - 3rd generation switch with three MACs and two - Broadband Gateway / Firewall / VPN PHYs fully compliant with IEEE 802.3u standard - Integrated DSL/Cable Modem - Non-blocking switch fabric assures fast packet - Wireless LAN access point + gateway delivery by utilizing an 1K MAC address lookup - Standalone 10/100 switch table and a store-and-forward architecture Revision 1.5 January 27, 2014 2