KS8995MA/FQ Integrated 5-Port 10/100 Managed Switch Rev. 3.0 General Description All PHY units support 10BASE-T and 100BASE-TX. The KS8995MA/FQ is a highly-integrated Layer 2 In addition, two of the PHY units support 100BASE-FX on managed switch with optimized bill of materials (BOM) ports 4 and 5 for KSZ8995MA, two of the PHY units cost for low port count, cost-sensitive 10/100Mbps switch support 100BASE-FX on ports 3 and 4 for KSZ8995FQ. systems with both copper and optic fiber media. It also provides an extensive feature set such as tag/port- Datasheets and support documentation can be found on based VLAN, quality of service (QoS) priority, Micrels web site at: www.micrel.com. management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KS8995MA/FQ contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. Functional Diagram Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KS8995MA/FQ Features Integrated switch with five MACs and five fast MDC and MDI/O interface support to access the MII Ethernet transceivers fully-compliant to IEEE 802.3u PHY control registers (not all control registers) standard MII local loopback support Shared memory based switch fabric with fully non- On-chip 64Kbyte memory for frame buffering (not blocking configuration shared with 1K unicast address table) 1.4Gbps high-performance memory bandwidth Wire-speed reception and transmission 10BASE-T, 100BASE-TX, and 100BASE-FX modes Integrated look-up engine with dedicated 1K MAC Dual MII configuration: MII-Switch (MAC or PHY addresses mode MII) and MII-P5 (PHY mode MII). Full duplex IEEE 802.3x and half-duplex back IEEE 802.1q tag-based VLAN (16 VLANs, full-range pressure flow control VID) for DMZ port, WAN/LAN separation or inter- Comprehensive LED support VLAN switch links 7-wire SNI support for legacy MAC interface VLAN ID tag/untag options, per-port basis Automatic MDI/MDI-X crossover for plug-and-play Programmable rate limiting 0Mbps to 100Mbps, Disable automatic MDI/MDI-X option ingress and egress port, rate options for high and low priority, per-port basis in 32Kbps increments Low power: Flow control or drop packet rate limiting Core: 1.8V (ingress port) Digital I/O: 3.3V Integrated MIB counters for fully-compliant statistics Analog I/O: 3.3V gathering, 34 MIB counters per port 0.18m CMOS technology Enable/Disable option for huge frame size up to Temperature ranges: 1916 bytes per frame Commercial: 0C to +70C IGMP v1/v2 snooping for multicast packet filtering Industrial: 40C to +85C Special tagging mode to send CPU info on ingress packets port value Available in 128-pin PQFP package SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register Applications configuration Broadband gateway/firewall/VPN MAC-id based security lock option Integrated DSL or cable modem multi-port router Control registers configurable on-the-fly (port- Wireless LAN access point plus gateway priority, 802.1p/d/q, AN...) Home networking expansion CPU read access to MAC forwarding table entries Standalone 10/100 switch 802.1d spanning tree protocol Hotel/campus/MxU gateway Port mirroring/monitoring/sniffing: ingress and/or Enterprise VoIP gateway/phone egress traffic to any port or MII FTTx customer premise equipment Broadcast storm protection with % control global Managed media converter and per-port basis Optimization for fiber-to-copper media conversion Full-chip hardware power-down support (register configuration not saved) Per-port based software power-save on PHY (idle link detection, register configuration preserved) QoS/CoS packets prioritization supports: Per port, 802.1p and DiffServ based 802.1p/q tag insertion or removal on a per-port basis (egress) December 2012 2 M9999-121212-3.0