FIFO, Flow Control, VLAN Tagging, Priority KS8995XA Integrated 5-Port 10/100 QoS Switch Rev 2.6 General Description The KS8995XA is a highly integrated Layer-2 quality of The KS8995XA contains five 10/100 transceivers with service (QoS) switch with optimized bill of materials patented mixed-signal low-power technology, five media (BOM) cost for low port count, cost-sensitive access control (MAC) units, a high-speed non-blocking 10/100Mbps switch systems. It also provides an switch fabric, a dedicated address lookup engine, and extensive feature set including three different QoS an on-chip frame buffer memory. priority schemes, a dual MII interface for BOM cost All PHY units support 10BASE-T and 100BASE-TX. In reduction, rate limiting to offload CPU tasks, software addition, two of the PHY units support 100BaseFX and hardware power-down, a MDC/MDIO control (Ports 4 and 5). interface and port mirroring/monitoring to effectively address both current and emerging Fast Ethernet applications. Functional Diagram 10/100 10/100 Auto 1K Look-Up MDI/MDI-X T/Tx 1 MAC 1 Engine 10/100 10/100 Auto T/Tx 2 MAC 2 MDI/MDI-X Queue Mgmnt 10/100 10/100 Auto T/Tx 3 MAC 3 MDI/MDI-X Buffer 10/100 10/100 Auto Mgmnt MDI/MDI-X T/Tx/Fx 4 MAC 4 10/100 10/100 Auto Frame T/Tx/Fx 5 MAC 5 MDI/MDI-X Buffers MII-P5 MDC, MDI/O SNI MII-SW or SNI LED0 5:1 LED1 5:1 LED I/F Control EEPROM LED2 5:1 Registers I/F KS8995XA Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KS8995XA Features Integrated switch with five MACs and five Fast Automatic address learning, address aging and address migration Ethernet transceivers fully compliant to IEEE 802.3u standard Full-duplex IEEE 802.3x and half-duplex back Shared memory based switch fabric with fully pressure flow control nonblocking configuration Comprehensive LED support 10BASE-T, 100BASE-TX and 100BASE-FX modes 7-wire SNI support for legacy MAC interface (FX in Ports 4 and 5) Automatic MDI/MDI-X crossover for plug-and-play Dual MII configuration: MII-Switch (MAC or PHY Disable automatic MDI/MDI-X option mode MII) and MII-P5 (PHY mode MII) Low power VLAN ID tag/untag options, per-port basis Core: 1.8V Enable/disable option for huge frame size up to 1916 Digital I/O: 3.3V bytes per frame Analog I/O: 2.5 or 3.3V Broadcast storm protection with percent control 0.18m CMOS technology global and per-port basis Commercial temperature range: 0C to +70C Optimization for fiber-to-copper media conversion Available in 128-pin PQFP package Full-chip hardware power-down support (register configuration not saved) Applications Per-port-based software power-save on PHY (idle Broadband gateway/firewall/VPN link detection, register configuration preserved) Integrated DSL or cable modem multi-port router QoS/CoS packets prioritization supports: per port, Wireless LAN access point plus gateway 802.1p and DiffServ-based Home networking expansion 802.1p/q tag insertion or removal on a per-port basis (egress) Standalone 10/100 switch Port-based VLAN support Hotel/campus/MxU gateway MDC and MDI/O interface support to access the MII Enterprise VoIP gateway/phone PHY control registers (not all control registers) FTTx customer premise equipment MII local loopback support Media converter On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) 1.4Gbps high performance memory bandwidth Wire-speed reception and transmission Integrated look-up engine with dedicated 1K unicast MAC addresses Ordering Information Part Number Temperature Range Package Standard Pb-Free KS8995XA KSZ8995XA 0C to +70C 128-Pin PQFP 2 September 2008 M9999-091508