FIFO, Flow Control, VLAN Tagging, Priority KS8995X Micrel KS8995X Integrated 5-Port 10/100 QoS Switch Rev. 1.13 General Description Features The KS8995X is a highly integrated Layer-2 QoS (Quality of Integrated switch with five MACs and five Fast Ethernet Service) switch with optimized BOM (Bill of Materials) cost for transceivers fully compliant to IEEE 802.3u standard low port count, cost-sensitive 10/100Mbps switch systems. It Shared memory based switch fabric with fully non- also provides an extensive feature set including three differ- blocking configuration ent QoS priority schemes, a dual MII interface for BOM cost 10BaseT, 100BaseTX and 100BaseFX modes (FX in reduction, rate limiting to offload CPU tasks, software and Ports 4 and 5) hardware power-down, a MDC/MDIO control interface and Dual MII configuration: MII-Switch (MAC or PHY mode port mirroring/monitoring to effectively address both current MII) and MII-P5 (PHY mode MII) and emerging Fast Ethernet applications. VLAN ID tag/untag options, per-port basis Enable/disable option for huge frame size up to 1916 The KS8995X contains five 10/100 transceivers with pat- bytes per frame ented mixed-signal low-power technology, five MAC (Media Broadcast storm protection with percent control global Access Control) units, a high-speed non-blocking switch and per-port basis fabric, a dedicated address lookup engine, and an on-chip Optimization for fiber-to-copper media conversion frame buffer memory. Full-chip hardware power-down support (register All PHY units support 10BaseT and 100BaseTX. In addition, configuration not saved) two of the PHY units support 100BaseFX (Ports 4 and 5). Per-port-based software power-save on PHY (idle link All support documentation can be found on Micrels web site detection, register configuration preserved) at www.micrel.com. QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based Functional Diagram 10/100 10/100 Auto 1K look-up MDI/MDIX T/Tx 1 MAC 1 Engine 10/100 10/100 Auto MDI/MDIX T/Tx 2 MAC 2 Queue Mgmnt Auto 10/100 10/100 MDI/MDIX T/Tx 3 MAC 3 Buffer 10/100 10/100 Auto Mgmnt T/Tx/Fx 4 MAC 4 MDI/MDIX 10/100 10/100 Auto Frame T/Tx/Fx 5 MAC 5 MDI/MDIX Buffers MII-P5 MDC, MDI/O SNI MII-SW or SNI LED0 5:1 LED1 5:1 LED I/F Control EEPROM LED2 5:1 Registers I/F Micrel, Inc. 1849 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 KS8995X Micrel Features (continued) Applications 802.1p/q tag insertion or removal on a per-port basis Broadband gateway/firewall/VPN (egress) Integrated DSL or cable modem multi-port router Port-based VLAN support Wireless LAN access point plus gateway MDC and MDI/O interface support to access the MII Home networking expansion PHY control registers (not all control registers) Standalone 10/100 switch MII local loopback support Hotel/campus/MxU gateway On-chip 64Kbyte memory for frame buffering (not Enterprise VoIP gateway/phone shared with 1K unicast address table) FTTx customer premise equipment 1.4Gbps high-performance memory bandwidth Media converter Wire-speed reception and transmission Integrated look-up engine with dedicated 1K unicast Ordering Information MAC addresses Automatic address learning, address aging and address Part Number Temperature Range Package migration KS8995X 0C to +70C 128-Pin PQFP Full-duplex IEEE 802.3x and half-duplex back pressure KSZ8995X 0C to +70C 128-Pin PQFP Lead Free flow control Comprehensive LED support 7-wire SNI support for legacy MAC interface Automatic MDI/MDI-X crossover for plug-and-play Disable automatic MDI/MDIX option Low power Core: 1.8V I/O: 2.5 or 3.3V 0.18 m CMOS technology Commercial temperature range: 0C to +70C Available in 128-pin PQFP package M9999-120403 2 December 2003