KSZ8864RMN Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces Rev 1.6 The KSZ8864RMN consists of 10/100 fast Ethernet PHYs General Description with patented and enhanced mixed-signal technology, The KSZ8864RMN is a highly-integrated, Layer 2 media access control (MAC) units, a high-speed non- managed 4-port switch with optimized design, plentiful blocking switch fabric, a dedicated address lookup engine, features and smallest package size. It is designed for cost- and an on-chip frame buffer memory. sensitive 10/100Mbps 4-port switch systems with on-chip The KSZ8864RMN contains four MACs and two PHYs. termination, lowest-power consumption, and small The two PHYs support the 10/100Base-T/TX. package to save system cost. It has 1.4Gbps high- All registers of MACs and PHYs units can be managed by performance memory bandwidth, shared memory-based the control interface of SPI or the SMI. MIIM registers of switch fabric with full non-blocking configuration. It also the PHYs can be accessed through the MDC/MDIO provides an extensive feature set such as the power 2 interface. EEPROM can set all control registers by I C management, programmable rate limiting and priority ratio, controller interface for the unmanaged mode. tag/port-based VLAN, packet filtering, quality of service (QoS), four queue prioritization, management interface, Datasheets and support documentation can be found on MIB counters. Port 3 and Port 4 support either MII or RMII Micrels website at: www.micrel.com. interfaces with SW3-MII/RMII and SW4-MII/RMII (see Functional Diagram) for KSZ8864RMN data interface. An industrial temperature-grade version of the KSZ8864RMNI and a qualified AEC-Q100 Automotive version of the KSZ8864RMNU are also available (see the Ordering Information section).The KSZ8864RMN provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. Functional Diagram Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8864RMN Integrated 4-Port 10/100 Ethernet Switch Features New generation switch with five MACs and five PHYs Advanced Switch Features that are fully compliant with the IEEE 802.3u standard. IEEE 802.1q VLAN support for up to 128 VLAN groups Non-blocking switch fabric assures fast packet delivery (full-range 4096 of VLAN IDs). by utilizing an 1K MAC address lookup table and a Static MAC table supports up to 32 entries. store-and-forward architecture. VLAN ID tag/untag options, per port basis. On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). Full-duplex IEEE 802.3x flow control (PAUSE) with force mode option. Programmable rate limiting at the ingress and egress on a per port basis. Half-duplex back pressure flow control. Jitter-free per packet based rate limiting support. HP Auto MDI/MDI-X and IEEE Auto crossover support. Broadcast storm protection with percentage control MII interface of MAC supports both MAC mode and (global and per port basis). PHY mode. IEEE 802.1d rapid spanning tree protocol RSTP Per port LED Indicators for link, activity, and 10/100 support. speed. Tail tag mode (1 byte added before FCS) support at Register port status support for link, activity, full/half Port 4 to inform the processor which ingress port duplex and 10/100 speed. receives the packet. On-chip terminations and internal biasing technology 1.4Gbps high-performance memory bandwidth and for cost down and lowest power consumption. shared memory based switch fabric with fully non- Switch Monitoring Features blocking configuration. Port mirroring/monitoring/sniffing: ingress and/or egress Dual MII/RMII with MAC 3 SW3-MII/RMII and MAC 4 traffic to any port or MII/RMII. SW4-MII/RMII interfaces. MIB counters for fully-compliant statistics gathering 34 Enable/Disable option for huge frame size up to 2000 MIB counters per port. Bytes per frame. Loop-back support for MAC, PHY and remote IGMP v1/v2 snooping (Ipv4) support for multicast diagnostic of failure. packet filtering. Interrupt for the link change on any ports. IPv4/IPv6 QoS support. Low-Power Dissipation: Support unknown unicast/multicast address and Full-chip software power-down and per port software unknown VID packet filtering. power down. Self-address filtering. Energy-detect mode support <0.1W full-chip power Comprehensive Configuration Register Access consumption when all ports have no activity. Serial management interface (MDC/MDIO) to all PHYs Very-low full-chip power consumption (<0.3W), without registers and SMI interface (MDC/MDIO) to all registers. extra power consumption on transformers. 2 High-speed SPI (up to 25MHz) and IC master Dynamic clock tree shutdown feature. Interface to all internal registers. Voltages: I/0 pins strapping and EEPROM to program selective Analog VDDAT 3.3V only. registers in unmanaged switch mode. VDDIO support 3.3V, 2.5V and 1.8V. Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN). Low 1.2V core power. QoS/CoS Packet Prioritization Support 0.13m CMOS technology. Per port, 802.1p and DiffServ-based. Commercial temperature range: 0C to +70C. 1/2/4-queue QoS prioritization selection. Industrial Temperature Range: 40C to +85C. Programmable weighted fair queuing for ratio control. Available in 64-pin QFN, lead-free small package Re-mapping of 802.1p priority field per port basis. March 26, 2015 2 Revision1.6