KSZ8895MLUB Integrated 5-Port 10/100 Managed Switch Revision 2.1 General Description The KSZ8895MLUB is a highly-integrated Layer 2- The KSZ8895MLUB consists of 10/100 PHYs with managed 5-port switch with an optimized design and patented and enhanced mixed-signal technology, media plentiful features, qualified to meet AEC-Q100 standard access control (MAC) units, a high-speed non-blocking for automotive applications. It is designed for cost- switch fabric, a dedicated address lookup engine, and an sensitive 10/100Mbps 5-port switch systems with on-chip on-chip frame buffer memory. The KSZ8895MLUB termination, lowest power consumption and internal core contains five MACs and four integrated PHYs. All PHYs power controller. These features will save more system support 10/100Base-T/TX. cost. It has 1.4Gbps high-performance memory All registers of MACs and PHYs units can be managed bandwidth, shared memory based switch fabric with full by the SPI interface or the SMI interface. MIIM registers non-blocking configuration. It also provides an extensive of the PHYs can be accessed through the MDC/MDIO feature set such as power management, programmable interface. EEPROM can set all control registers for the rate limit and priority ratio, tag/port-based VLAN, packets unmanaged mode. filtering, quality-of-service (QoS) four-queue The KSZ8895MLUB provides multiple CPU control/data prioritization, management interface, and MIB counters. interfaces to effectively address both current and Port 5 is a MAC 5 MII interface with PHY mode as emerging fast Ethernet applications. default at switch side. The SW5-MII interface can be Datasheets and support documentation are available on connected to a processor with a MAC MII interface. Micrels web site at: www.micrel.com. Functional Diagram Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8895MLUB Features Advanced Switch Features Integrated 5-Port 10/100 Ethernet Switch IEEE 802.1q VLAN support for up to 128 VLAN groups New generation switch with five MACs and five PHYs fully (full-range 4096 of VLAN IDs). compliant with IEEE 802.3u standard. Static MAC table supports up to 32 entries. Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and a store-and- VLAN ID tag/untag options, per port basis. forward architecture. IEEE 802.1p/q tag insertion or removal on a per port On-chip 64Kbyte memory for frame buffering (not shared with basis based on ingress port (egress). 1K unicast address table). Programmable rate limiting at the ingress and egress on Full duplex IEEE 802.3x flow control (PAUSE) with force mode a per port basis. option. Jitter-free per packet based rate-limiting support. Half-duplex back pressure flow control. Broadcast storm protection with percentage control HP Auto MDI/MDI-X and IEEE Auto crossover support. (global and per port basis). Port 5 MAC5 SW5-MII interface supports PHY mode and MAC IEEE 802.1d rapid spanning tree protocol RSTP mode. support. 7-wire serial network interface (SNI) support for legacy MAC. Tail tag mode (1byte added before FCS) support at Port 5 to inform the processor which ingress port receives Per port LED Indicators for link, activity, and 10/100 speed. the packet. Register port status support for link, activity, full/half duplex 1.4Gbps high-performance memory bandwidth and and 10/100 speed. shared memory-based switch fabric with fully non- Micrel LinkMD cable diagnostic capabilities for blocking configuration. determining cable opens, shorts, and length. MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII On-chip terminations and internal biasing technology for cost interface. down and lowest power consumption. Enable/Disable option for huge frame size up to 2000 Switch Monitoring Features bytes per frame. Port mirroring/monitoring/sniffing: ingress and/or egress traffic IGMP v1/v2 snooping (Ipv4) support for multicast packet to any port or MII. filtering. MIB counters for fully-compliant statistics gathering 34 MIB IPv4/IPv6 QoS support. counters per port. Support unknown unicast/multicast address and Loop-back support for MAC, PHY, and remote diagnostic of unknown VID packet filtering. failure. Self-address filtering. Interrupt for the link change on any ports. Comprehensive Configuration Register Access Low Power Dissipation Serial management interface (MDC/MDIO) to all PHYs Full-chip hardware power-down. registers and SMI interface (MDC/MDIO) to all registers. Full-chip software power-down/per port software power down. 2 High-speed SPI (up to 25MHz) and I C master Interface Energy-detect mode support < 100mW full-chip power to all internal registers. consumption when all ports have no activity. I/0 pins strapping and EEPROM to program selective Very-low, full-chip power consumption (<0.5W), without extra registers in unmanaged switch mode. power consumption on transformers. Control registers configurable on the fly (port-priority, Dynamic clock-tree shutdown feature. 802.1p/d/q, AN). Voltages: Single 3.3V supply with 3.3V VDDIO and Internal QoS/CoS Packet Prioritization Support 1.2V LDO controller enabled or external 1.2V LDO solution: Per port, 802.1p and DiffServ-based. Analog VDDAT 3.3V only 1/2/4-queue QoS prioritization selection. VDDIO support 3.3V, 2.5V and 1.8V Programmable weighted fair queuing for ratio control. Low 1.2V core power Re-mapping of 802.1p priority field per port basis. o o Industrial Temperature Range: 40 C to +85 C. Available in 128-pin LQFP, lead-free package. Applications In-vehicle diagnostics (OBD) High-speed software download Gateway switch Head unit Rear seat entertainment April 1, 2014 2 Revision 2.1