LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Reduced Power Modes Highlights - Numerous power management modes Optimized for the highest data-rate applications - Wake on LAN* such as high-definition video and multi-media - Magic packet wakeup* applications - Wakeup indicator event signal Efficient architecture with low CPU overhead - Link Status Change Easily interfaces to most 32-bit and 16-bit embed- Single chip Ethernet controller ded CPUs - Fully compliant with IEEE 802.3/802.3u stan- Integrated PHY dards Supports audio & video streaming over Ethernet: - Integrated Ethernet MAC and PHY multiple high-definition (HD) MPEG2 streams - 10BASE-T and 100BASE-TX support Pin compatible with other members of LAN9118 - Full- and Half-duplex support - Full-duplex flow control family (LAN9117, LAN9116 and LAN9115) - Backpressure for half-duplex flow control Target Applications - Preamble generation and removal - Automatic 32-bit CRC generation and check- Video distribution systems, multi-room PVR ing High-end Cable, satellite, and IP set-top boxes - Automatic payload padding and pad removal Digital video recorders - Loop-back modes High definition televisions Flexible address filtering modes Digital media clients/servers - One 48-bit perfect address Home gateways - 64 hash-filtered multicast addresses - Pass all multicast Key Benefits - Promiscuous mode - Inverse filtering Supports highest performance applications - Pass all incoming with status report - Highest performing non-PCI Ethernet control- - Disable reception of broadcast packets ler in the market Integrated Ethernet PHY - 32-bit interface with fast bus cycle times - Burst-mode read support - Auto-negotiation - Automatic polarity detection and correction Eliminates dropped packets High-Performance host bus interface - Internal buffer memory can store over 200 packets - Simple, SRAM-like interface - Supports automatic or host-triggered PAUSE - 32/16-bit data bus and back-pressure flow control - Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions Minimizes CPU overhead - One configurable host interrupt - Supports Slave-DMA Miscellaneous features - Interrupt Pin with Programmable Hold-off timer - Low profile 100-pin, TQFP RoHS Compliant package Reduces system cost and increases design flexi- - Integral 1.8V regulator bility - General Purpose Timer - SRAM-like interface easily interfaces to most - Support for optional EEPROM embedded CPUs or SoCs - Support for 3 status LEDs multiplexed with - Low-cost, low--pin count non-PCI interface Programmable GPIO signals for embedded designs 3.3V Power Supply with 5V tolerant I/O 0 to 70 C * Third-party brands and names are the property of their respective owners. 2005-2018 Microchip Technology Inc. DS00002266B-page 1LAN9118 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
