MCP2517FD-H/JHA Microchip

MCP2517FD External CAN FD Controller with SPI Interface Oscillator Options Features 40, 20 or 4 MHz crystal, or ceramic resonator or General external clock input External CAN FD Controller with SPI Interface Clock output with prescaler Arbitration Bit Rate up to 1 Mbps SPI Interface Data Bit Rate up to 8 Mbps Up to 20 MHz SPI clock speed CAN FD Controller modes Supports SPI modes 0,0 and 1,1 - Mixed CAN 2.0B and CAN FD mode Registers and bit fields are arranged in a way to - CAN 2.0B mode enable efficient access via SPI Conforms to ISO 11898-1:2015 Safety Critical Systems Message FIFOs SPI commands with CRC to detect noise on SPI 31 FIFOs, configurable as transmit or receive interface FIFOs Error Correction Code (ECC) protected RAM One Transmit Queue (TXQ) Additional Features Transmit Event FIFO (TEF) with 32 bit time stamp GPIO pins: INT0 and INT1 can be configured as Message Transmission general purpose I/O Message transmission prioritization: Open drain outputs: TXCAN, INT, INT0, and INT1 - Based on priority bit field, and/or pins can be configured as push/pull or open drain - Message with lowest ID gets transmitted first outputs using the Transmit Queue (TXQ) Package Types Programmable automatic retransmission MCP2517FD attempts: unlimited, 3 attempts or disabled SOIC14 Message Reception 32 Flexible Filter and Mask Objects TXCAN 1 14 VDD Each object can be configured to filter either: RXCAN 2 13 nCS - Standard ID + first 18 data bits, or CLKO/SOF 3 12 SDO - Extended ID INT 4 11 SDI 32-bit Time Stamp OSC2 5 10 SCK 6 9 OSC1 INT0/GPIO0/XSTBY Special Features 7 8 VSS INT1/GPIO1 VDD: 2.7 to 5.5V Active current: max. 20 mA at 5.5 V, 40 MHz CAN MCP2517FD clock VDFN14 with wettable flanks* Sleep current: 10 A, typical TXCAN 1 14 VDD Message objects are located in RAM: 2 KB 2 13 RXCAN nCS Up to 3 configurable interrupt pins CLKO/SOF 3 12 SDO Bus Health Diagnostics and Error counters EP* INT 4 11 SDI Transceiver standby control OSC2 5 10 SCK Start of frame pin for indicating the beginning of messages on the bus OSC1 6 9 INT0/GPIO0/XSTBY Temperature ranges: VSS 7 8 INT1/GPIO1 - High (H): 40C to +150C *VDFN14 includes an Exposed Thermal Pad (EP) see Table 1-1 2017-2018 Microchip Technology Inc. DS20005688B-page 1MCP2517FD 1.0 DEVICE OVERVIEW 1.1 Block Diagram The MCP2517FD is a cost-effective and Figure 1.1 shows the block diagram of the small-footprint CAN FD controller that can be easily MCP2517FD. The MCP2517FD contains the following added to a microcontroller with an available SPI main blocks: interface. Therefore, a CAN FD channel can be easily The CAN FD Controller module implements the added to a microcontroller that is either lacking a CAN CAN FD protocol and contains the FIFOs, and Fil- FD peripheral, or that doesnt have enough CAN FD ters. channels. The SPI interface is used to control the device by The MCP2517FD supports both, CAN frames in the accessing SFRs and RAM. Classical format (CAN2.0B) and CAN Flexible Data The RAM controller arbitrates the RAM accesses Rate (CAN FD) format, as specified in ISO 11898- between the SPI and CAN FD Controller module. 1:2015. The Message RAM is used to store the data of the Message Objects. The oscillator generates the CAN clock. The Internal LDO and POR circuit. The I/O control. Note 1: This data sheet summarizes the features of the MCP2517FD. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the MCP25xxFD Family Reference Manual. FIGURE 1-1: MCP2517FD BLOCK DIAGRAM VDD nCS Internal SPI LDO SCK VSS Interface SDI POR SDO CLKO/SOF I/O Message RAM RAM Controller INT INT0/GPIO0/XSTBY INT1/GPIO1 OSC1 CAN FD Oscillator Controller RXCAN RX OSC2 Module Filter TXCAN DS20005688B-page 2 2017-2018 Microchip Technology Inc.