MCP37231/21-200 MCP37D31/21-200 200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX Digital Signal Post-Processing (DSPP) Options: Features: - Decimation Filters for improved SNR Sample Rates: - Fractional Delay Recovery (FDR) for time- - 200 Msps for single-channel mode delay corrections in multi-channel operations - 200 Msps/Number of channel used (dual/octal-channel modes) SNR with f = 15 MHz and -1 dBFS: IN - Phase, Offset and Gain adjust of individual - >74 dBFS for 200 Msps channels SFDR with f = 15 MHz and -1 dBFS: IN - Digital Down-Conversion (DDC) with I/Q or - >90 dBFS at 200 Msps f /8 output (MCP37D31/21-200) S Power Dissipation with LVDS Digital I/O: - Continuous Wave Beamforming for octal- channel mode (MCP37D31/21-200) - 490 mW for 200 Msps Built-In ADC Linearity Calibration Algorithms: Power Dissipation with CMOS Digital I/O: - Harmonic Distortion Correction (HDC) - 436 mW for 200 Msps, Output Clock = 100 MHz - DAC Noise Cancellation (DNC) Power Dissipation Excluding Digital I/O: - Dynamic Element Matching (DEM) - 390 mW for 200 Msps - Flash Error Calibration Power Saving modes: Serial Peripheral Interface (SPI) - 80 mW during Standby Package Options: - 33 mW during Shutdown - VTLA-124 (9 mm x 9 mm x 0.9 mm) Supply Voltage: - TFBGA-121 (8 mm x 8 mm x 1.08 mm) - Digital Section: 1.2V, 1.8V No External Reference Decoupling Capacitor - Analog Section: 1.2V, 1.8V Required for TFBGA Package Selectable Input Range: up to 2.98 V P-P Industrial Temperature Range: -40C to +85C Input Channel Bandwidth: 500 MHz Channel-to-Channel Crosstalk: >95 dB in Typical Applications: Multi-Channel mode (Input = 15 MHz, -1 dBFS) Output Data Format: Communication Instruments - Parallel CMOS, DDR LVDS Cellular Base Stations - Serialized DDR LVDS (16-bit, octal-channel mode) Radar Optional Output Data Randomizer Ultrasound and Sonar Imaging Scanners and Low-Power Portable Instruments Industrial and Consumer Data Acquisition System Device Offering (Note 1): Digital Part Number Sample Rate Resolution Decimation CW Beamforming Down-Conversion MCP37231-200 200 Msps 16 Yes No No MCP37221-200 200 Msps 14 Yes No No MCP37D31-200 200 Msps 16 Yes Yes Yes MCP37D21-200 200 Msps 14 Yes Yes Yes Note 1: For 14-bit devices and TFBGA package, contact Microchip Technology Inc. for availability. The devices in the same package type are pin-compatible. 2014 Microchip Technology Inc. DS20005322A-page 1MCP37231/21-200 AND MCP37D31/21-200 Functional Block Diagram AV AV GND DV DV DD12 DD18 DD12 DD18 Duty Cycle DLL CLK+ Clock Correction Selection CLK- PLL DCLK+ Output Clock Control DCLK- A + IN0 Digital Signal Post-Processing: A - IN0 Pipelined - FDR, Decimation ADC - Phase/Offset/Gain Adj. MCP37D31/21-200: A + IN7 - DDC, CW Beamforming A - IN7 WCK V V REF+ REF- OVR Output Control: V CM - CMOS, DDR LVDS - Serialized LVDS Reference Q 15:0 SENSE Generator Internal Registers V BG REF1+ REF1- REF0+ REF0- SDIO SCLK CS DS20005322A-page 2 2014 Microchip Technology Inc. Input Multiplexer