MCP37D11-80 80 Msps, 12-Bit High-Precision Pipelined ADC Digital Signal Post-Processing (DSPP) Options: Features - Decimation filters for improved SNR Sample Rates: - Fractional Delay Recovery (FDR) for time- - 80 Msps for single-channel operation delay corrections in multi-channel operations - 80 Msps/number of channels used - Noise-Shaping Requantizer (NSR) SNR with f = 15 MHz and -1 dBFS: IN - Phase, Offset and Gain adjust of individual - 70.9 dBFS (typical) at 80 Msps channels SFDR with f = 15 MHz and -1 dBFS: IN - Digital Down-Conversion (DDC) - 92.2 dBc (typical) at 80 Msps - Continuous wave (CW) beamforming for Power Dissipation with LVDS Digital I/O: octal-channel mode - 311 mW at 80 Msps Serial Peripheral Interface (SPI) Power Dissipation with CMOS Digital I/O: Auto Sync Mode to synchronize multiple devices - 248 mW at 80 Msps, Output Clock = 80 MHz to the same clock Power Dissipation Excluding Digital I/O: TFBGA-121 package - 229 mW at 80 Msps - Dimension: 8 mm x 8 mm x 1.08 mm Power-Saving Modes: - Includes embedded decoupling capacitors for - 79 mW during Standby reference pins and bandgap output pin - 22 mW during Shutdown AEC-Q100 Qualified (Automotive Applications) Supply Voltage: - Temperature Grade 1: -40C to +125C - Digital Section: 1.2V, 1.8V - Analog Section: 1.2V, 1.8V Typical Applications Selectable Full-Scale Input Range: up to 2.975 V P-P Configurable 8-Channel Input MUX: Communication Instruments - Single-Channel or Sequential Multi-Channel Microwave Digital Radio Sampling Lidar and Radar Input Channel Bandwidth: 500 MHz High-Speed Test Equipment Output Data Format: Ultrasound and Sonar Imaging - Parallel CMOS, DDR LVDS Scanners and Low-Power Portable Instruments Optional Output Data Randomizer Industrial and Consumer Data Acquisition Systems Built-In ADC Linearity Calibration Algorithms: - Harmonic Distortion Correction (HDC) - DAC Noise Cancellation (DNC) - Dynamic Element Matching (DEM) - Flash Error Calibration (1) MCP37Dx1-80 Family Comparison : Digital Digital CW Noise-Shaping Part Number Sample Rate Resolution (3) (3) (4) (2) Decimation Down-Conversion Beamforming Requantizer MCP37D11-80 80 Msps 12 Yes Yes Yes Yes MCP37D21-80 80 Msps 14 Yes Yes Yes No (5) MCP37D31-80 80 Msps 16 Yes Yes Yes No Note 1: All devices are pin-to-pin compatible. 2: Available in single- and dual-channel modes. 3: Available in single- and dual-channel modes, and octal-channel mode when CW beamforming is enabled. 4: Available in octal-channel mode. 5: 18-bit output is available in MCP37D31-80 with high-order decimation filter setting. 2020 Microchip Technology Inc. DS20006381A-page 1MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC Functional Block Diagram AV AV GND DV DV DD12 DD18 DD12 DD18 Duty Cycle DLL CLK+ Clock Correction Selection CLK- PLL DCLK+ Output Clock Control DCLK- Digital Signal Post-Processing: (Selectable using Configuration Register Bits) A + IN0 - Digital Down-Converter (DDC) A - IN0 - Decimation Filter Pipelined - Fractional Delay Recovery (FDR) ADC - Noise-Shaping Requantizer (NSR) A + IN7 - Continuous Wave (CW) Beamforming A - - Phase/Offset/Gain Adjustment IN7 V V REF+ REF- WCK Output Control: OVR V Output CM - CMOS, DDR LVDS Data - Serialized LVDS 11:0 Q Reference Generator SENSE Configuration Registers V BG REF1+ REF1- REF0- SDIO SCLK CS SYNC SLAVE REF0+ Note 1 Note 1: All external circuit components for REF0/1 and V pins are already embedded in the TFBGA-121 package. BG DS20006381A-page 2 2020 Microchip Technology Inc. Input Multiplexer