MCP37D31-80 AND MCP37D21-80 80 Msps, 16/14-Bit High-Precision Pipelined ADC Digital Signal Post-Processing (DSPP) Options: Features - Decimation filters for improved SNR Sample Rates: - Fractional Delay Recovery (FDR) for time- - 80 Msps for single-channel operation delay corrections in multi-channel operations - 80 Msps/number of channels used - Phase, Offset and Gain adjust of individual SNR with f = 15 MHz and -1 dBFS: IN channels - 73.9 dBFS (typical) at 80 Msps - Digital Down-Conversion (DDC) SFDR with f = 15 MHz and -1 dBFS: IN - Continuous wave beamforming for octal- - 93 dBc (typical) at 80 Msps channel mode Power Dissipation Excluding Digital I/O (80 Msps): Serial Peripheral Interface (SPI) -229mW Auto Sync Mode to synchronize multiple devices Power Dissipation with CMOS Digital I/O (80 Msps): to the same clock - MCP37D31-80: 257 mW TFBGA-121 Package - MCP37D21-80: 253 mW - Dimension: 8 mm x 8 mm x 1.08 mm Power Dissipation with LVDS Digital I/O (80 Msps): - Includes embedded decoupling capacitors for - MCP37D31-80: 329 mW reference pins and bandgap output pin - MCP37D21-80: 320 mW AEC-Q100 Qualified (Automotive Applications) Power-Saving Modes: - Temperature Grade 1: -40C to +125C - 79 mW during Standby - 22 mW during Shutdown Typical Applications Supply Voltage: - Digital Section: 1.2V, 1.8V Communication Instruments - Analog Section: 1.2V, 1.8V Microwave Digital Radio Selectable Full-Scale Input Range: up to 2.975 V P-P Lidar and Radar Configurable 8-Channel Input MUX: High-Speed Test Equipment - Single-Channel or Sequential Multi-Channel Ultrasound and Sonar Imaging Sampling Scanners and Low-Power Portable Instruments Input Channel Bandwidth: 500 MHz Output Data Format: Industrial and Consumer Data Acquisition Systems - Parallel CMOS, DDR LVDS - Serialized DDR LVDS (16-bit, octal-channel mode) Optional Output Data Randomizer Built-In ADC Linearity Calibration Algorithms: - Harmonic Distortion Correction (HDC) - DAC Noise Cancellation (DNC) - Dynamic Element Matching (DEM) - Flash Error Calibration (1) MCP37Dx1-80 Family Comparison : Digital Digital CW Noise-Shaping Part Number Sample Rate Resolution (3) (3) (4) (2) Decimation Down-Conversion Beamforming Requantizer (5) MCP37D31-80 80 Msps 16 Yes Yes Yes No MCP37D21-80 80 Msps 14 Yes Yes Yes No MCP37D11-80 80 Msps 12 Yes Yes Yes Yes Note 1: All devices are pin-to-pin compatible. 2: Available in single and dual-channel modes. 3: Available in single and dual-channel modes, and octal-channel mode when CW beamforming is enabled. 4: Available in octal-channel mode. 5: 18-bit output is available in MCP37D31-80 with high-order decimation filter setting. 2020 Microchip Technology Inc. DS20006382A-page 1MCP37D31-80 AND MCP37D21-80 Functional Block Diagram AV AV GND DV DV DD12 DD18 DD12 DD18 Duty Cycle DLL CLK+ Clock Correction Selection CLK- PLL DCLK+ Output Clock Control DCLK- Digital Signal Post-Processing: (Selectable using Configuration Register Bits) A + IN0 - Digital Down-Converter (DDC) A - IN0 Pipelined - Decimation Filter ADC - Fractional Delay Recovery (FDR) A + - Continuous Wave (CW) Beamforming IN7 - Phase/Offset/Gain Adjustment A - IN7 V V REF+ REF- WCK Output Control: (0.9V) OVR V Output CM - CMOS, DDR LVDS Data - Serialized LVDS 15:0 Reference Generator Q SENSE Configuration Registers DM1 DM2 Note 2 V SYNC SLAVE BG REF1+ REF1- REF0+ REF0- SDIO SCLK CS Note 1 Note 1: All external circuit components for REF0/1 and V pins are already embedded in the TFBGA-121 package. BG Note 2: DM1 and DM2 are extra output data pins for the 18-bit output mode, which is only available with the MCP37D31-80. DS20006382A-page 2 2020 Microchip Technology Inc. Input Multiplexer