MEC1428-NU-C1

MEC142x Keyboard and Embedded Controller Products for Notebook PC System to EC Message Interface Common Features - One Embedded Memory Interface 3.3V and 1.8V Operation - Host Serial or Parallel IRQ Source ACPI 3.0 Compliant - Provides Two Windows to On-Chip SRAM for VTR (standby) and VBAT Power Planes Host Access - Low Standby Current in Sleep Mode - Two Register Mailbox Command Interface Configuration Register Set - Mailbox Registers Interface - Compatible with ISA Plug-and-Play Standard - Thirty-two 8-Bit Scratch Registers - EC-Programmable Base Address - Two Register Mailbox Command Interface MIPS32 M14K Microcontroller Core - Two Register SMI Source Interface - microMIPS-Compatible Instruction Set - Five ACPI Embedded Controller Interfaces - High-performance Multiply/Divide Unit - Four EC Interfaces - Programmable clock frequencies: 48MHz, - One Power Management Interface 12MHz, 3MHz, and 1MHz 8042 Emulated Keyboard Controller -Sleep mode - 8042 Style Host Interface - 2-wire Debug Interface (ICSP) - Port 92 Legacy A20M Support - 6 Breakpoints (4-instruction 2-data) - Fast GATEA20 & Fast CPU RESET - Enhanced to Support Debug in Heavy and Vectored Interrupt Controller Deep Sleep States - Maskable Interrupt controller Secure Boot ROM Loader - Maskable Hardware Wake-Up Events - 2 Code Images in Shared Flash Supported - Supports legacy aggregated mode - Crisis Recovery over Keyboard matrix Scan Pins - Supports Vector Generation per Status Bit - Supports CRC-32 and AES-128 Encryption Battery Backed Resources Enhanced Serial Peripheral Interface (eSPI) - VBAT-Powered Control Interface (VCI) - Intel eSPI Specification compliant - 2 Active-low VCI Inputs - Support for Slave Attached Flash Sharing - 1 Active-high VCI Input (SAFS) - 1 Active-high VCI Output Pin - Support for Master Attached Flash Sharing (MAFS) - Optional filter and latching - Supports four channels/interfaces: - Power-Fail Status Register - Peripheral channel Interface - 64 Bytes Battery Powered SRAM - Virtual Wire Interface - Battery-Powered General Purpose Output (BGPO) - Out of Band Channel Interface 32kHz Clock Source - Flash Channel Interface - Internal 32kHz Oscillator - Supports EC Bus Master to Host Memory - External 32kHz Clock Source - Supports up to 66 MHz maximum operating fre- quency - 32kHz Crystal (XTAL) Supported LPC Host Interface - Single-Ended 32kHz Clock Source - LPC Specification 1.1 Compatible Trace FIFO Debug Port (TFDP) - LPC I/O and Memory Cycles Decoded Internal DMA Controller - Supports optional signals: CLKRUN , LPCPD , - Hardware or Firmware Flow Control SERIRQ, SMI , EC SCI (ACPI PME Event) - Firmware Initiated Memory-to-Memory transfers - Supports 19.2 MHz to 33 MHz nominal bus clock - 11-Hardware DMA Channels support five SMBus speeds 2017 Microchip Technology Inc. DS00002343C-page 1MEC142x Master/Slave Controllers and one SPI Controller - System Power Present Input Pin - Hardware CRC-32 Generator on Channel 0 - Week Alarm Event only generated when Sys- tem Power is Available Programmable 16-bit Timer - Power-up Event - Four 16-bit Auto-restarting Timer Instances - Week Alarm Interrupt with 1 Second to 8.5 Year - Two Operating Modes per Instance: Continuous Time-out and One-shot. - Sub-Week Alarm Interrupt with 0.50 Seconds - 32-bit RTOS Timer 72.67 hours time-out - Runs Off 32kHz Clock Source - 1 Second and Sub-second Interrupts - Continues Counting in all the Chip Sleep States Port 80 BIOS Debug Port Regardless of Processor Sleep State - Two Ports, Assignable to Any LPC IO Address - Counter is Halted when Embedded Controller is Halted (e.g., JTAG debugger active, break - 24-bit Timestamp with Adjustable Timebase points) - 16-Entry FIFO - Generates wake-capable interrupt event PECI Interface 3.0 Watch Dog Timer (WDT) Two Programmable Comparators Hibernation Timer Interface - Independent Outputs per Comparator - One 32.768 KHz Driven Timer - Voltage Reference Input Pin - Programmable Wake-up from 0.5ms to 128 Min- - Can be used for Thermistor Voltage Sensing utes Integrated Standby Power Reset Generator Week Timer XNOR Test Mode Product Dependent Features Internal Memory - PS/2 Edge Wake Capable - Boot ROM - 3.6V Tolerant I/O Suitable for Internal Board Routing - 32 kB Data Optimized SRAM General Purpose I/O Pins - Code Optimized SRAM Options from 96 kB to 160 kB - Inputs - 64 Bytes Battery Powered SRAM - Asynchronous rising and falling edge wakeup detection Interrupt High or Low Level Keyboard Matrix Scan Controller -Outputs: - Supports 18x8 Matrix - Push Pull or Open Drain output - Pre-Drive Mode Supported - Programmable power well emulation Up To Five EC-based SMBus 2.0 Host Controllers - Pull up or pull down resistor control - Allows Master or Dual Slave Operation - Automatically disabling pull-up resistors when - Controllers are Fully Operational on Standby output driven low Power 2 - Automatically disabling pull-down resistors C Datalink Compatibility Mode -I when output driven high - Multi-Master Capable - Group- or individual control of GPIO data - Supports Clock Stretching - Over voltage and under voltage support (not all - Programmable Bus Speeds pins have both) - 1 MHz Capable - Two regions of configurable 1.8V or 3.3V I/O - SMBus Time-outs Interface Up To Three LEDs - Up to 7 Port Flexible Multiplexing - Programmable Blink Rates - Up to 6 ports with 1.8V or 3.3V Configurable - Piecewise Linear Breathing LED Output Control- Input Threshold ler - 1 port with VTT level signaling (i.e., AMD SB- - Provides for programmable rise and fall TSI Port) waveforms - Supports DMA Network Layer - Operational in EC Sleep States Up To Two PS/2 Controllers One Serial Peripheral Interface (SPI) Controller - Independent Hardware Driven PS/2 Ports - Master Only SPI Controller - Fully functional on Main and/or Suspend Power - Mappable to three ports (only 1 port active at a DS00002343C-page 2 2017 Microchip Technology Inc.