MT88L89ASR1 Microchip

MT88L89 3 V Integrated DTMF Transceiver with Adaptive Micro Interface Data Sheet February 2011 Features Complete DTMF transmitter/receiver Ordering Information Low voltage operation (2.7-3.6 V) MT88L89AP1 28 Pin PLCC* Tubes MT88L89AN1 24 Pin SSOP* Tubes Pin for pin compatible with existing MT8880, MT88L89AS1 20 Pin SOIC* Tubes MT8888 and MT8889 devices MT88L89ANR1 24 Pin SSOP* Tape & Reel MT88L89ASR1 20 Pin SOIC* Tape & Reel Adaptive micro interface enables compatibility with Intel and Motorola processors *Pb Free Matte Tin -40 C to +85 C DTMF transmitter/receiver power-down via register control Adjustable guard time The receiver section is based upon the industry Automatic tone burst mode standard MT8870 DTMF receiver. The transmitter Call progress tone detection to -30 dBm utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal Applications counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress Credit card systems filter can be selected allowing a microprocessor to Paging systems analyze call progress tones. Repeater systems/mobile radio The MT88L89 utilizes an adaptive micro interface, Interconnect dialers which allows the device to be connected to a number of popular microcontrollers with minimal external logic. Pay phones The MT88L89 provides enhanced power-down Remote monitor/Control systems features. The transmitter and receiver may independently be powered down via register control. Description The MT88L89 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. D0 Data Row and D/A Transmit Data Bus Column D1 TONE Converters Register Buffer Counters D2 D3 Status Interrupt Tone Burst Control Register Gating Cct. Logic Logic IRQ/CP Control IN+ + Dial Register Tone - High Group IN- A Digital Filter DS/RD Filter Algorithm GS Control and Code I/O CS Converter Register Low Group Control OSC1 B Filter Oscillator R/W/WR Circuit OSC2 RS0 Control Receive Data Steering Bias Logic Register Logic Circuit V V V ESt St/GT DD Ref SS Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2011, Zarlink Semiconductor Inc. All Rights Reserved.MT88L89 Data Sheet Change Summary The following table reflects the changes from the September 2005 revision to the February 2011 revision. Page Item Description 1 Ordering Information Removed leaded parts. IN+ 1 24 VDD 1 20 IN+ VDD 2 23 IN- St/GT 2 19 IN- St/GT 22 GS 3 ESt 18 GS 3 ESt NC NC 21 5 25 VRef 4 D3 17 VRef 4 D3 NC VRef 5 20 6 24 VSS D2 5 16 VSS D2 NC VSS 7 23 19 OSC1 6 D1 15 OSC1 6 D1 OSC1 D3 8 22 18 OSC2 7 D0 14 OSC2 D2 OSC2 7 D0 9 21 17 NC 8 NC D1 TONE 13 NC 10 20 8 IRQ/CP 16 NC 9 NC D0 NC 11 19 R/W/WR 12 9 DS/RD TONE 15 10 IRQ/CP CS 11 10 RS0 14 R/W/WR 11 DS/RD 13 CS 12 RS0 20 PIN /PLASTIC DIP/SOIC 24 PIN SSOP 28 PIN PLCC Figure 2 - Pin Connections Pin Description Pin Name Description 20 24 28 111 IN+ Non-inverting op-amp input. 222 IN- Inverting op-amp input. 334 GS Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 446 V Reference Voltage output (V /2). Ref DD 557 V Ground (0 V). SS 668 OSC1 Oscillator input. This pin can also be driven directly by an external clock. CMOS compatible. 779 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. 8 10 12 TONE Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register A (CRA) is set to low. Requires resistive termination to V . SS 911 13 R/W (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible. (WR) 10 12 14 CS Chip Select input must be gated externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, depending on processor used. See Figure 12. Must not be tied low. CMOS compatible. 2 Zarlink Semiconductor Inc. 12 4 13 3 14 2 15 1 16 28 17 27 18 26 GS NC IN- IN+ VDD St/GT EST DS/RD TONE R/W/WR CS RS0 NC IRQ/CP