PIC18(L)F25/26K83 28-Pin, Low-Power, High-Performance Microcontrollers with CAN Technology Description The PIC18(L)FXXK83 is a full-featured CAN product family that can be used in automotive and industrial applications. 2 The multitude of communication peripherals found on the product family, such as CAN, SPI, two I Cs, two UARTs, LIN, DMX, and DALI can handle a wide range of wired and wireless (using external modules) communication protocols for 2 ) extensions for automated signal intelligent applications. This family includes a 12-bit ADC with Computation (ADC analysis to reduce the complexity of the application. This, combined with the Core Independent Peripherals integration capabilities, enables functions for motor control, power supply, sensor, signal and user interface applications. Core Features Memory C Compiler Optimized RISC Architecture Up to 64 KB Flash Program Memory Operating Speed: Up to 4 KB Data SRAM Memory - Up to 64 MHz clock operation Up to 1 KB Data EEPROM - 62.5 ns minimum instruction cycle Memory Access Partition (MAP): Two Direct Memory Access (DMA) Controllers: - Configurable boot and app region sizes with individual write-protections - Data transfers to SFR/GPR spaces from either Program Flash Memory, Data Programmable Code Protection EEPROM or SFR/GPR spaces Device Information Area (DIA) stores: - User-programmable source and destination - Unique IDs and Device IDs sizes - Temp Sensor factory-calibrated data - Hardware and software-triggered data - Fixed Voltage Reference calibrated data transfers Device Configuration Information (DCI) stores: System Bus Arbiter with User-Configurable - Erase row size Priorities for Scanner and DMA1/DMA2 with - Number of write latches per row respect to the main line and interrupt execution - Number of user rows Vectored Interrupt Capability: - Data EEPROM memory size - Selectable high/low priority - Pin count - Fixed interrupt latency - Programmable vector table base address Operating Characteristics 31-Level Deep Hardware Stack Operating Voltage Range: Low-Current Power-on Reset (POR) - 1.8V to 3.6V (PIC18LF25/26K83) Configurable Power-up Timer (PWRT) - 2.3V to 5.5V (PIC18F25/26K83) Brown-Out Reset (BOR) Temperature Range: Low-Power BOR (LPBOR) Option - Industrial: -40C to 85C Windowed Watchdog Timer (WWDT): - Extended: -40C to 125C - Variable prescaler selection - Variable window size selection - Configurable in hardware or software Power-Saving Functionality DOZE mode: Ability to run CPU core slower than the system clock IDLE mode: Ability to halt CPU core while internal peripherals continue operating SLEEP mode: Lowest power consumption Peripheral Module Disable (PMD): - Ability to disable unused peripherals to minimize power consumption 2017 Microchip Technology Inc. Preliminary DS40001943A-page 1PIC18(L)F25/26K83 One SPI module: eXtreme Low-Power (XLP) Features - Configurable length bytes Sleep mode: 60 nA 1.8V, typical - Configurable length data packets Windowed Watchdog Timer: 720 nA 1.8V, - Receive-without-transmit option typical - Transmit-without-receive option Secondary Oscillator: 580 nA 32 kHz - Transfer byte counter Operating Current: - Separate Transmit and Receive Buffers with - 4 uA 32 kHz, 1.8V, typical 2-byte FIFO and DMA capabilities - 45 uA/MHz 1.8V, typical CAN module: - Conforms to CAN 2.0B Active Specification Digital Peripherals - Three operating modes: Legacy (compatible with existing PIC18CXX8/FXX8 CAN modules), Three 8-Bit Timers (TMR2/4/6) with Hardware Enhanced mode, and FIFO mode. Limit Timer (HLT): - Message bit rates up to 1 Mbps - Hardware monitoring and Fault detection - DeviceNet data byte filter support Four 16-Bit Timers (TMR0/1/3/5) - Six programmable receive/transmit buffers Four Configurable Logic Cell (CLC): - Three dedicated transmit buffers - Integrated combinational and sequential logic - Two dedicated receive buffers Three Complementary Waveform Generators (CWGs): - 16 Full, 29-bit acceptance filters with dynamic association - Rising and falling edge dead-band control - Three full, 29-bit acceptance masks - Full-bridge, half-bridge, 1-channel drive - Automatic remote frame handling - Multiple signal sources - Advanced error management features. - Programmable dead band 2 Two I C modules, SMBus, PMBus compatible: - Fault-shutdown input - Dedicated Address, Transmit and Receive Four Capture/Compare/PWM (CCP) modules buffers Four 10-bit Pulse-Width Modulators (PWMs) - Bus Collision Detection with arbitration Numerically Controlled Oscillator (NCO): - Bus time-out detection and handling - Generates true linear frequency control - Multi-Master mode - High resolution using 20-bit accumulator and - Separate Transmit and Receive Buffers with 20-bit increment values 2-byte FIFO and DMA capabilities DSM: Data Signal Modulator: 2 -I C, SMBus 2.0 and SMBus 3.0, and 1.8V - Multiplex two carrier clocks, with glitch pre- input level selections vention feature Device I/O Port Features: - Multiple sources for each carrier - 25 I/O pins (PIC18(L)F25K83) Programmable CRC with Memory Scan: - One input-only pin - Reliable data/program memory monitoring for - Individually programmable I/O direction, fail-safe operation (e.g., Class B) open-drain, slew rate, weak pull-up control - Calculate CRC over any portion of program - Interrupt-on-change memory - Three External Interrupt Pins Two UART Modules: Peripheral Pin Select (PPS): - Modules are Asynchronous, RS-232, RS-485 - Enables pin mapping of digital I/O compatibility. Two Signal Measurement Timer (SMT): - One of the UART modules supports LIN Master and Slave, DMX mode, DALI Gear - 24-bit timer/counter with prescaler and Device protocols - Automatic and user-timed BREAK period generation - DMA Compatible - Automatic checksums - Programmable 1, 1.5, and two Stop bits - Wake-up on BREAK reception 2017 Microchip Technology Inc. Preliminary DS40001943A-page 2