PIC18F97J94 FAMILY 8-Bit LCD Flash Microcontroller with USB and XLP Technology Hardware Real-Time Clock/Calendar (RTCC): eXtreme Low-Power Features - Runs in Deep Sleep and VBAT modes Multiple Power Management Options for Extreme Two Master Synchronous Serial Ports (MSSP) Power Reduction: modules Featuring: -VBAT allows for lowest power consumption on - 3-Wire/4-Wire SPI (all 4 modes) back-up battery (with or without RTCC) - SPI Direct Memory Access (DMA) channel - Deep Sleep allows near total power-down with the w/1024 byte count 2 ability to wake-up on external triggers -Two I C modules Support Multi-Master/Slave - Sleep and Idle modes selectively shut down mode and 7-Bit/10-Bit Addressing peripherals and/or core for substantial power Four Enhanced Addressable USART modules: reduction and fast wake-up - Support RS-485, RS-232 and LIN/J2602 Alternate Clock modes Allow On-the-Fly Switching to - On-chip hardware encoder/decoder for IrDA a Lower Clock Speed for Selective Power Reduction - Auto-wake-up on Auto-Baud Detect Extreme Low-Power Current Consumption for Digital Signal Modulator Provides On-Chip OOK, Deep Sleep: FSK and PSK Modulation for a Digital Signal Stream - WDT: 650 nA 2V typical High-Current Sink/Source 18 mA/18 mA on all Digital I/O - RTCC: 650 nA 32 kHz, 2V typical Configurable Open-Drain Outputs on ECCP/CCP/ - Deep Sleep current, 80 nA typical USART/MSSP Extended Microcontroller mode Using 12, 16 or 20-Bit Addressing mode Universal Serial Bus Features USB V2.0 Compliant Analog Features Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) Supports Control, Interrupt, Isochronous and Bulk 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Transfers Converter: Supports up to 32 Endpoints (16 bidirectional) - Conversion rate of 500 ksps (10-bit), USB module can use Any RAM Location on the 200 kbps (12-bit) Device as USB Endpoint Buffers - Conversion available during Sleep and Idle On-Chip USB Transceiver Three Rail-to-Rail Enhanced Analog Comparators with Programmable Input/Output Configuration On-Chip Programmable Voltage Reference Peripheral Features Charge Time Measurement Unit (CTMU): LCD Display Controller: - Used for capacitive touch sensing, up to - Up to 60 segments by 8 commons 24 channels - Internal charge pump and low-power, internal - Time measurement down to 1 ns resolution resistor biasing - CTMU temperature sensing - Operation in Sleep mode Up to Four External Interrupt Sources Peripheral Pin Select Lite (PPS-Lite): High-Performance CPU - Allows independent I/O mapping of many High-Precision PLL for USB peripherals Two External Clock modes, Up to 64 MHz Four 16-Bit and Four 8-Bit Timers/Counters with (16 MIPS ) Prescaler Internal 31 kHz Oscillator Seven Capture/Compare/PWM (CCP) modules Three Enhanced Capture/Compare/PWM (ECCP) High-Precision Internal Oscillator with Clock modules: Recovery from SOSC to Achieve 0.15% Precision, - One, two or four PWM outputs 31 kHz to 8 MHz or 64 MHz w/PLL, - Selectable polarity 0.15% Typical, 1.5% Max. - Programmable dead time Secondary Oscillator using Timer1 32 kHz - Auto-shutdown and auto-restart C Compiler Optimized Instruction Set Architecture - Pulse steering control Two Address Generation Units for Separate Read and Write Addressing of Data Memory 2012-2016 Microchip Technology Inc. DS30000575C-page 1PIC18F97J94 FAMILY Power-on Reset (POR), Power-up Timer (PWRT) Special Microcontroller Features and Oscillator Start-up Timer (OST) Operating Voltage Range of 2.0V to 3.6V Brown-out Reset (BOR) with Operation Below VBOR, Two On-Chip Voltage Regulators (1.8V and 1.2V) for with Regulator Enabled Regular and Extreme Low-Power Operation High/Low-Voltage Detect (HLVD) 20,000 Erase/Write Cycle Endurance Flash Program Flexible Watchdog Timer (WDT) with its Own Memory, Typical RC Oscillator for Reliable Operation Flash Data Retention: 10 Years Minimum Standard and Ultra Low-Power Watchdog Timers Self-Programmable under Software Control (WDT) for Reliable Operation in Standard and Deep Two Configurable Reference Clock Outputs Sleep modes (REFO1 and REFO2) In-Circuit Serial Programming (ICSP) Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator TABLE 1: PIC18F97J94 FAMILY TYPES Memory Remappable Peripherals Device PIC18F97J94 100 128K 4K 4 4 2 3 Y 2 24 Y 480 Y Y Lite PIC18F87J94 80 128K 4K 4 4 2 3 Y 2 24 Y 352 Y Y Lite PIC18F67J94 64 128K 4K 4 4 2 3 Y 2 16 Y 224 Y Y Lite PIC18F96J94 100 64K 4K 4 4 2 3 Y 2 24 Y 480 Y Y Lite PIC18F86J94 80 64K 4K 4 4 2 3 Y 2 24 Y 352 Y Y Lite PIC18F66J94 64 64K 4K 4 4 2 3 Y 2 16 Y 224 Y Y Lite PIC18F95J94 100 32K 4K 4 4 2 3 Y 2 24 Y 480 Y Y Lite PIC18F85J94 80 32K 4K 4 4 2 3 Y 2 24 Y 352 Y Y Lite PIC18F65J94 64 32K 4K 4 4 2 3 Y 2 16 Y 224 Y Y Lite For other small form-factor package availability and marking information, visit