PIC24FJ128GA204 FAMILY 28/44-Pin, General Purpose, 16-Bit Flash Microcontrollers with Cryptographic Engine, ISO 7816 and XLP Technology Cryptographic Engine Extreme Low-Power Features (Continued) AES Engine with 128,192 or 256-Bit Key Alternate Clock modes allow On-the-Fly Switching to a Lower Clock Speed for Selective Supports ECB, CBC, OFB, CTR and Power Reduction CFB128 modes Extreme Low-Power Current Consumption for DES/Triple DES (TDES) Engine: Supports Deep Sleep: 2-Key and 3-Key EDE or DED TDES - WDT: 270 nA 3.3V typical Supports up to Three Unique Keys for TDES - RTCC: 400 nA 32 kHz, 3.3V typical Programmatically Secure - Deep Sleep current: 40 nA, 3.3V typical Pseudorandom Number Generator True Random Number Generator Analog Features Non-Readable, On-Chip, OTP Key Storages 10/12-Bit, 13-Channel Analog-to-Digital (A/D) Converter: Extreme Low-Power Features - Conversion rate of 500 ksps (10-bit), Multiple Power Management Options for Extreme 200 ksps (12-bit) Power Reduction: - Conversion available during Sleep and Idle -VBAT allows the device to transition to a Three Rail-to-Rail, Enhanced Analog Comparators backup battery for the lowest power with Programmable Input/Output Configuration consumption with RTCC Three On-Chip Programmable Voltage References - Deep Sleep allows near total power-down Charge Time Measurement Unit (CTMU): with the ability to wake-up on internal or - Used for capacitive touch sensing, up to 13 channels external triggers - Time measurement down to 100 ps resolution - Sleep and Idle modes selectively shut down - Operation in Sleep mode peripherals and/or core for substantial power reduction and fast wake-up - Doze mode allows CPU to run at a lower clock speed than peripherals Analog Memory Digital Peripherals Peripherals Device PIC24FJ128GA204 128K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y PIC24FJ128GA202 128K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y PIC24FJ64GA204 64K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y PIC24FJ64GA202 64K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y 2013-2015 Microchip Technology Inc. DS30010038C-page 1 Program Flash (bytes) Data RAM (bytes) Pins 10/12-Bit A/D (ch) Comparators CTMU (ch) Input Capture Output Compare/PWM 2 I C SPI UART w/IrDA 7816 EPMP/PSP 16-Bit Timers Deep Sleep w/VBAT AES/DES CryptographicPIC24FJ128GA204 FAMILY Peripheral Features High-Performance CPU Up to Five External Interrupt Sources Modified Harvard Architecture Peripheral Pin Select (PPS) Allows Independent Up to 16 MIPS Operation 32 MHz I/O Mapping of Many Peripherals 8 MHz Internal Oscillator: Five 16-Bit Timers/Counters with Prescaler: - 96 MHz PLL option - Can be paired as 32-bit timers/counters - Multiple clock divide options Six-Channel DMA supports All Peripheral modules: - Run-time self-calibration capability for - Minimizes CPU overhead and increases data maintaining better than 0.20% accuracy throughput - Fast start-up Six Input Capture modules, Each with a 17-Bit x 17-Bit Single-Cycle Hardware Dedicated 16-Bit Timer Fractional/Integer Multiplier Six Output Compare/PWM modules, Each with a 32-Bit by 16-Bit Hardware Divider Dedicated 16-Bit Timer 16 x 16-Bit Working Register Array Enhanced Parallel Master/Slave Port (EPMP/EPSP) C Compiler Optimized Instruction Set Hardware Real-Time Clock/Calendar (RTCC): Architecture (ISA) - Runs in Sleep, Deep Sleep and VBAT modes Two Address Generation Units (AGUs) for Three 3-Wire/4-Wire SPI modules: Separate Read and Write Addressing of Data Memory - Support four Frame modes - Variable FIFO buffer 2 Special Microcontroller Features -I S mode - Variable width from 2-bit to 32-bit Supply Voltage Range of 2.0V to 3.6V 2 Two I C modules Support Multi-Master/Slave Two On-Chip Voltage Regulators (1.8V and 1.2V) mode and 7-Bit/10-Bit Addressing for Regular and Extreme Low-Power Operation Four UART modules: 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical - Support RS-485, RS-232 and LIN/J2602 Flash Data Retention: 20 Years Minimum - On-chip hardware encoder/decoder for IrDA - Smart Card ISO 7816 support on UART1 and Self-Programmable under Software Control UART2 only: Programmable Reference Clock Output - T = 0 protocol with automatic error handling In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via 2 Pins - T = 1 protocol JTAG Programming and Boundary Scan Support - Dedicated Guard Time Counter (GTC) - Dedicated Waiting Time Counter (WTC) Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, - Auto-wake-up on Auto-Baud Detect (ABD) Low-Power RC Oscillator (LPRC) - 4-level deep FIFO buffer Power-on Reset (POR), Power-up Timer (PWRT) Programmable 32-Bit Cyclic Redundancy Check and Oscillator Start-up Timer (OST) (CRC) Generator Separate Brown-out Reset (BOR) and Deep Digital Signal Modulator provides On-Chip FSK Sleep Brown-out Reset (DSBOR) Circuits and PSK Modulation for a Digital Signal Stream Programmable High/Low-Voltage Detect (HLVD) High-Current Sink/Source (18 mA/18 mA) on Flexible Watchdog Timer (WDT) with its Own All I/O Pins RC Oscillator for Reliable Operation Configurable Open-Drain Outputs on Digital I/O Pins Standard and Ultra Low-Power Watchdog Timers 5.5V Tolerant Inputs on Most Pins (ULPWs) for Reliable Operation in Standard and Deep Sleep modes DS30010038C-page 2 2013-2015 Microchip Technology Inc.