PIC32MK0512GPD064-I/PT Microchip

PIC32MK GENERAL PURPOSE AND MOTOR CONTROL (GPG/MCJ) WITH CAN FD FAMILY 32-bit General Purpose and Motor Control Application MCUs with CAN FD, FPU, ECC Flash, and up to 512 KB Flash, 64 KB SRAM, and Op amps Operating Conditions: 2.3V to 3.6V Security Features -40C to +85C, DC to 120 MHz Advanced Memory Protection: -40C to +125C, DC to 80 MHz - Peripheral and memory region access control Core: 120 MHz (up to 198 DMIPS) Advanced Analog Features MIPS32 microAptiv MCU core with Floating Point Unit 12-bit ADC module: microMIPS mode for up to 40% smaller code size - Sum of all individual ADCs combined, 25.45 Msps 12-bit DSP-enhanced core: mode or 33.79 Msps 8-bit mode - Four 64-bit accumulators - 7 individual ADC modules - Single-cycle MAC, saturating and fractional math - 3.75 Msps per S&H with dedicated DMA Code-efficient (C and Assembly) architecture - Up to 30 analog inputs Two 32-bit core register files to reduce interrupt latency Flexible and independent ADC trigger sources Four high bandwidth op-amps and five comparators Clock Management Up to two 12-bit CDACs Internal temperature sensor 2C accuracy 8 MHz 4% (FRC) internal oscillator -40C to +85C Capacitive Touch Divider (CVD) Programmable PLLs and oscillator clock sources: - HS and EC clock modes Communication Interfaces 32 kHz Internal Low-power RC oscillator (LPRC) Independent external low-power 32 kHz crystal oscillator CAN Flexible Data-Rate (CAN FD) module (with dedicated DMA Fail-Safe Clock Monitor (FSCM) channels): Independent Watchdog Timers (WDT) and Deadman Timer - 2.0B Active with DeviceNet addressing support (DMT) - ISO 11898-1:2015 compliant Fast wake-up and start-up Up to two UART modules (up to 25 Mbps): Four Fractional clock out (REFCLKO) modules - Supports LIN 2.1 and IrDA protocols 2 Two SPI/I S modules (SPI 50 Mbps) Power Management 2 Two I C modules (up to 1 Mbaud) with SMBus support Low-power management modes (Sleep, and Idle) Peripheral Pin Select (PPS) to enable remappable pin functions Integrated: - Power-on Reset (POR) and Brown-out Reset (BOR) Timers/Output Compare/Input Capture/RTCC - Programmable High/Low Voltage Detect (HLVD) Up to nine 16-bit or one 16-bit and eight 32-bit timers/counters On-board capacitorless regulator for GP and MC devices and two additional QEI 32-bit timers for Motor Control PWM MC devices 9 Output Compare (OC) modules Up to nine PWM pairs 9 Input Capture (IC) modules Leading-edge and Trailing-edge blanking PPS to enable function remap Dead Time for rising and falling edges Real-Time Clock and Calendar (RTCC) module Dead Time Compensation 8.33 ns PWM Resolution Input/Output Clock Chopping for High-Frequency Operation 5V-tolerant pins with up to 22 mA source/sink PWM Support for: Selectable internal open drain, pull-ups, and pull-downs - DC/DC, AC/DC, inverters, PFC, lighting External interrupts on all I/O pins - BLDC, PMSM, ACIM, SRM motors Five programmable edge/level-triggered interrupt pins Choice of 10 Fault and 9 Current Limit Inputs Flexible Trigger Configuration for ADC Triggering Qualification and Class B Support Motor Encoder Interface AEC-Q100 Grade 1 (-40C to 125C) Three Quadrature Encoder Interface (QEI) modules: Class B Safety Library - Four inputs: Phase A, Phase B, Home, and Index Back-up internal oscillator Clock monitor with back-up internal oscillator Audio/Graphics/Touch Interfaces Global register locking 2 Up to two I S audio data communication interfaces Debugger Development Support Up to two SPI control interfaces Programmable host clock: In-circuit and in-application programming - Generation of fractional clock frequencies 2-wire or 4-wire MIPS Enhanced JTAG interface - Can be tuned in run-time Unlimited software and 12 complex breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Unique Features Non-intrusive hardware-based instruction trace Permanent non-volatile 4-word unique device serial number Flash Error Code Correction (ECC) Software and Tools Support C/C++ compiler with native DSP/fractional support Direct Memory Access (DMA) MPLAB Harmony Integrated Software Framework Up to eight channels with automatic data size detection TCP/IP, Graphics, and mTouch middleware Programmable Cyclic Redundancy Check (CRC) MFi, Android and Bluetooth audio frameworks Up to 64 KB transfers RTOS Kernels: Express Logic ThreadX, FreeRTOS, OPENRTOS , Micrim C/OS, and SEGGER embOS 2019-2021 Microchip Technology Inc. DS60001570D -page 1PIC32MK GPG/MCJ with CAN FD Family Packages Type VQFN QFN TQFP Pin Count 48 64 48 64 I/O Pins (up to) 37 53 37 53 Contact/Lead Pitch 0.4 mm 0.50 mm 0.5 mm 0.50 mm Dimensions 6 x 6 x 0.9 mm 9 x 9 x 1 mm 7 x 7 x 0.9 mm 10 x 10 x 1 mm DS60001570D-page 2 2019-2021 Microchip Technology Inc.