PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU, Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog Operating Conditions Advanced Analog Features 2.1V to 3.6V, -40C to +85C, DC to 252 MHz 12-bit ADC module: 2.1V to 3.6V, -40C to +125C, DC to 180 MHz - 18 Msps with up to six Sample and Hold (S&H) circuits (five dedicated and one shared) Core: 252 MHz (up to 415 DMIPS) M-Class - Up to 48 analog inputs 16 KB I-Cache, 4 KB D-Cache - Can operate during Sleep and Idle modes FPU for 32-bit and 64-bit floating point math - Multiple trigger sources MMU for optimum embedded OS execution - Six Digital Comparators and six Digital Filters microMIPS mode for up to 35% smaller code size Two comparators with 32 programmable voltage DSP-enhanced core: references - Four 64-bit accumulators Temperature sensor with 2C accuracy - Single-cycle MAC, saturating, and fractional math Communication Interfaces - IEEE 754-compliant Two CAN modules (with dedicated DMA channels): Code-efficient (C and Assembly) architecture - 2.0B Active with DeviceNet addressing support Clock Management Six UART modules (25 Mbps): Programmable PLLs and oscillator clock sources - Supports up to LIN 2.1 and IrDA protocols Fail-Safe Clock Monitor (FSCM) Six 4-wire SPI modules (up to 50 MHz) Independent Watchdog Timers (WDT) and Deadman SQI configurable as an additional SPI module (50 MHz) 2 Timer (DMT) Five I C modules (up to 1 Mbaud) with SMBus support Parallel Master Port (PMP) Fast wake-up and start-up Peripheral Pin Select (PPS) to enable function remap Power Management Timers/Output Compare/Input Capture Low-power modes (Sleep and Idle) Integrated Power-on Reset (POR) and Brown-out Reset Nine 16-bit or up to four 32-bit timers/counters Nine Output Compare (OC) modules (BOR) Nine Input Capture (IC) modules Memory Interfaces Real-Time Clock and Calendar (RTCC) module 50 MHz External Bus Interface (EBI) Input/Output 50 MHz Serial Quad Interface (SQI) 5V-tolerant pins with up to 32 mA source/sink Audio and Graphics Interfaces Selectable open drain, pull-ups, pull-downs, and slew rate Graphics interfaces: EBI or PMP controls 2 Audio data communication: I S, LJ, and RJ External interrupts on all I/O pins 2 PPS to enable function remap Audio control interfaces: SPI and I C Audio master clock: Fractional clock frequencies with USB Qualification and Class B Support synchronization AEC-Q100 REVH (Grade 1 -40C to +125C) High-Speed (HS) Communication Interfaces Class B Safety Library, IEC 60730 (planned) (with Dedicated DMA) Back-up internal oscillator USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller Debugger Development Support 10/100 Mbps Ethernet MAC with MII and RMII interface In-circuit and in-application programming Security Features 4-wire MIPS Enhanced JTAG interface Unlimited software and 12 complex breakpoints Crypto Engine with RNG for data encryption/decryption and IEEE 1149.2-compatible (JTAG) boundary scan authentication (AES, 3DES, SHA, MD5, and HMAC) Non-intrusive hardware-based instruction trace Advanced memory protection: - Peripheral and memory region access control Software and Tools Support C/C++ compiler with native DSP/fractional and FPU support Direct Memory Access (DMA) MPLAB Harmony Integrated Software Framework Eight channels with automatic data size detection TCP/IP, USB, Graphics, and mTouch middleware Programmable Cyclic Redundancy Check (CRC) MFi, Android, and Bluetooth audio frameworks RTOS Kernels: Express Logic ThreadX, FreeRTOS, OPENRTOS , Micrim C/OS, and SEGGER embOS Packages Type QFN TQFP VTLA LQFP TFBGA (1) Pin Count 64 64 100 144 100 144 124 144 I/O Pins (up to) 53 53 78 120 78 120 98 120 Contact/Lead Pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.40 mm 0.65 mm 0.50 mm 0.50 mm 0.50 mm Dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm Note 1: Contact your local Microchip Sales Office for information on the availability of devices in the 100-pin TFBGA packages 2015-2018 Microchip Technology Inc. DS60001320E-page 1PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320E-page 2 2015-2018 Microchip Technology Inc. TABLE 1: PIC32MZ EF FAMILY FEATURES Remappable Peripherals PIC32MZ0512EFE064 0N Y 8/12 PIC32MZ0512EFF064 512 128 2N Y 8/16 PIC32MZ0512EFK064 2Y Y 8/18 TQFP, 64 160 34 9/9/9 6 4 5 24 2 Y 4 Y N Y Y Y 46 Y Y QFN PIC32MZ1024EFE064 0N Y 8/12 PIC32MZ1024EFF064 1024 256 2 N Y 8/16 PIC32MZ1024EFK064 2Y Y 8/18 PIC32MZ0512EFE100 0N Y 8/12 PIC32MZ0512EFF100 512 128 2N Y 8/16 PIC32MZ0512EFK100 2Y Y 8/18 100 TQFP 160 51 9/9/9 6 6 5 40 2 Y 5 Y Y Y Y Y 78 Y Y PIC32MZ1024EFE100 0N Y 8/12 PIC32MZ1024EFF100 1024 256 2 N Y 8/16 PIC32MZ1024EFK100 2Y Y 8/18 PIC32MZ0512EFE124 0N Y 8/12 PIC32MZ0512EFF124 512 128 2N Y 8/16 PIC32MZ0512EFK124 2Y Y 8/18 124 VTLA 160 53 9/9/9 6 6 5 48 2 Y 5 Y Y Y Y Y 97 Y Y PIC32MZ1024EFE124 0N Y 8/12 PIC32MZ1024EFF124 1024 256 2 N Y 8/16 PIC32MZ1024EFK124 2Y Y 8/18 PIC32MZ0512EFE144 0N Y 8/12 PIC32MZ0512EFF144 512 128 2N Y 8/16 LQFP, PIC32MZ0512EFK144 2Y Y 8/18 144 TQFP, 160 53 9/9/9 6 6 5 48 2 Y 5 Y Y Y Y Y 120 Y Y PIC32MZ1024EFE144 0N Y 8/12 TFBGA PIC32MZ1024EFF144 1024 256 2N Y 8/16 PIC32MZ1024EFK144 2Y Y 8/18 Note 1: Eight out of nine timers are remappable. 2: Four out of five external interrupts are remappable. 3: This device is available with a 252 MHz speed rating. Device Program Memory (KB) Data Memory (KB) Pins Packages Boot Flash Memory (KB) Remappable Pins Timers/ Capture/ (1) Compare UART 2 SPI/I S External (2) Interrupts CAN 2.0B Crypto RNG DMA Channels (Programmable/ Dedicated) ADC (Channels) Analog Comparators USB 2.0 HS OTG 2 I C PMP EBI SQI RTCC Ethernet I/O Pins JTAG Trace