PL123-05SI Microchip

PL123-05 PL123-09 PL123-05/-09 Low Skew Zero Delay Buffer FEATURES DESCRIPTION Frequency Range 10MHz to 134 MHz The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers Output Options: designed to distribute high speed clocks. They have o 5 outputs PL123-05 one (PL123-05) or two (PL123-09) low-skew output o 9 outputs PL123-09 banks, of 4 outputs each, that are synchronized with Zero input - output delay the input. The PL123-09 allows control of the banks of Optional Drive Strength: outputs by using the S1 and S2 inputs as shown in the Standard (8mA) PL123-05/-09 Selector Definition table on page 2. High (12mA) PL123-05H/-09H 3.3V, 10% operation The synchronization is established via CLKOUT feed Available in Commercial and Industrial temperature back to the input of the PLL. Since the skew between ranges the input and output is less than 100ps, the device Available in 16-Pin SOP or TSSOP (PL123-09), acts as a zero delay buffer. The input output propaga- and 8-Pin SOP (PL123-05) packages tion delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant ap- plications. BLOCK DIAGRAM REF 1 8 CLKOUT REF CLKOUT PLL Mux CLKA2 2 7 CLKA4 CLKA1 CLKA1 3 6 VDD GND 4 5 CLKA3 CLKA2 CLKA3 REF 1 16 CLKOUT CLKA4 CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 CLKB1 VDD 4 13 VDD S1 Selector GND 5 12 GND CLKB2 Inputs CLKB1 6 11 CLKB4 S2 (PL123-09 Only) CLKB3 CLKB2 7 10 CLKB3 S2 8 9 S1 CLKB4 Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 4/22/13 Page 1 Bank B Bank A PL123-05/-09 Low Skew Zero Delay Buffer PIN DESCRIPTIONS PL123-09 PL123-05 Name Type Description TSSOP-16L SOP-16L SOP-8L 1 REF 1 1 1 I Input reference frequency. 2 CLKA1 2 2 3 O Buffered clock output, Bank A 2 CLKA2 3 3 2 O Buffered clock output, Bank A VDD 4,13 4,13 6 P VDD connection GND 5,12 5,12 4 P GND connection 2 CLKB1 6 6 - O Buffered clock output, Bank B 2 CLKB2 7 7 - O Buffered clock output, Bank B 3 S2 8 8 - I Selector input 3 S1 9 9 - I Selector input 2 CLKB3 10 10 - O Buffered clock output, Bank B 2 CLKB4 11 11 - O Buffered clock output, Bank B 2 CLKA3 14 14 5 O Buffered clock output, Bank A 2 CLKA4 15 15 7 O Buffered clock output, Bank A Buffered clock output. Internal feedback 2 CLKOUT 16 16 8 O on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2 SELECTOR DEFINITION FOR PL123-09 CLOCK A1 A4 CLOCK B1 B4 S2 S1 CLKOUT Output Source PLL Shutdown (Bank A) (Bank B) 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CONTROL The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust- ments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 4/22/13 Page 2