PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
FEATURES DESCRIPTION
2 LVCMOS Outputs The PL133-27 is an advanced fanout buffer design for
high performance, low-power, small form-factor
Input/Output Frequency: 1MHz to 150MHz
applications. The PL133-27 accepts a reference
Supports LVCMOS or Sine Wave Input Clock
clock input of 1MHz to 150MHz and produces two
Extremely low additive Jitter
outputs of the same frequency. Reference clock
8 mA Output Drive Strength
inputs may be LVCMOS or sine-wave signals (the
Low Current Consumption
inputs are internally AC-coupled). PL133-27 is
Single 1.8V, 2.5V, or 3.3V, 10% Power Supply
designed to fit in a small 2 x 1.3 x 0.6mm DFN
Operating Temperature Range
package, and offers the best phase noise and jitter
o 0C to 70C (Commercial)
performance and lowest power consumption of any
o -40 C to 85 C (Industrial)
comparable IC.
Available in DFN-6L GREEN/RoHS Compliant
Packages
PACKAGE PIN CONFIGURATION
FIN 1 6 OE
CLK1 2 5 VDD
GND 3 4 CLK0
DFN-6L
(2.0 x 1.3 x 0.6mm)
BLOCK DIAGRAM
CLK0
FIN
CLK1
OE
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 09/13/13 Page 1 PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
PACKAGE PIN ASSIGNMENT
Package Pin #
Name Type Description
DFN-6L
FIN 1 I Reference clock input
CLK1 2 O Clock output
GND 3 P GND connection
CLK0 4 O Clock output
VDD 5 P V connection
DD
OE 6 I Output enable input
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations
- Keep traces short! - Place decoupling capacitors as close as possible to
the V pin(s) to limit noise from the power supply
DD
- Trace = Inductor. With a capacitive load this equals
ringing! - Multiple V pins should be decoupled separately
DD
for best performance.
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing). - Addition of a ferrite bead in series with V can
DD
help prevent noise from other board sources
- Design long traces as striplines or microstrips with
defined impedance. - Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1 F for
- Match trace at one side to avoid reflections bouncing
designs using crystals < 50MHz and 0.01 F for
back and forth.
designs using crystals > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
(Typical buffer impedance 20)
50 line
Series Resistor
Use value to match output buffer impedance to
50 trace. Typical value 30
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 09/13/13 Page 2