PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC FEATURES DESCRIPTION The PL133-47 is an advanced fanout buffer design for 1:4 LVCMOS output fanout buffer for DC to150MHz high performance, low-power, small form factor applica- Low Additive Phase Jitter of 60fs RMS tions. The PL133-47 accepts a reference clock input from 8mA Output Drive Strength DC to 150MHz and provides 4 outputs of the same fre- Low power consumption for portable applications quency. Low input-output delay The PL133-47 is offered in a SOP-8L package and it offers Output-Output skew less than 250ps the best phase noise, additive jitter performance, and low- 2.5V to 3.3V, 10% operation est power consumption of any comparable IC. Operating temperature range from -40C to 85C Available in 8-Pin SOP GREEN/RoHS package BLOCK DIAGRAM AND PACKAGE PINOUT VDD 1 8 CLK3 CLK0 7 VDD 2 CLK2 CLK1 REF 3 6 CLK1 REF CLK2 GND 4 5 CLK0 CLK3 SOP-8L Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/1 Page 1 PL133-47 Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC PIN DESCRIPTIONS Name SOP-8L Type Description REF 3 I Input reference frequency. CLK0 5 O Buffered clock output CLK1 6 O Buffered clock output CLK2 7 O Buffered clock output CLK3 8 O Buffered clock output VDD 1, 2 P VDD connection GND 4 P GND connection LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB d esign: Signal Integrity and Termination Decoupling and Power Supply Considerations Considerations - Keep traces short - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power - Trace = Inductor. With a capacitive load this equals supply ringing - Addition of a ferrite bead in series with VDD can - Long trace = Transmission Line. Without proper termi- help prevent noise from other board sources nation this will cause reflections ( looks like ringing ). - Value of decoupling capacitor is frequency de- - Design long traces (> 1 inch) as striplines or pendant. Typical values to use are 0.1 F for de- microstrips with defined impedance. signs using frequencies < 50MHz and 0.01 F for - Match trace at one side to avoid refl ections bouncing designs using frequencies > 50MHz. back and forth. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 ohm) 50 ohm line Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 1/27/11 Page 2