UTOPIA Level 2/POS-PHY Level 2 System Interface APSO +/- Path Crossbar/ APSI +/- APS Crossconnect APECLV Serial Line Interface PM5384 Released S/UNI 1x155 Single Channel OC-3c ATM and POS Physical Layer Device Provides control circuitry required to Provides a generic 8-bit FEATURES comply with Bellcore GR-253-CORE microprocessor bus interface for Single chip ATM and Packet over WAN clocking requirements related to configuration, control, and status SONET/SDH Physical Layer Device wander transfer, holdover, and long- monitoring. operating at 155.52 Mbit/s. term stability when using an external Low power 2.5/3.3 V CMOS with 5 V Implements the ATM Forum User VCXO. TTL-compatible digital inputs/outputs Network Interface (UNI) and the ATM Provides a UTOPIA Level 2, 8-bit wide (PECL inputs/outputs are 3.3 V and physical layer for Broadband ISDN system interface (clocked up to 5 V compatible). according to ITU Recommendation 52 MHz) with parity support for ATM Industrial temperature range (-40C to I.432. applications. +85C). Implements Point-to-Point Protocol Provides a UTOPIA Level 2, 16-bit 15 mm x15 mm 196-pin stPBGA (PPP) over SONET/SDH according to wide system interface (clocked up to package with 1 mm ball pitch. RFC 2615. 52 MHz) with parity support for ATM Processes duplex bit-serial 155.52 applications. Mbit/s STS-3c/STM-1 data streams APPLICATIONS Provides a SATURN POS-PHY with on-chip clock and data recovery Level 2, 16-bit system interface Routers and Layer 3 Switches. and clock synthesis. (clocked up to 52 MHz) for Packet over 3G Wireless Base Station Controllers. Complies with Bellcore GR-253-CORE SONET/SDH (POS) applications DSLAM Uplinks. (2000 Issue) jitter tolerance, jitter (similar to UTOPIA Level 2, but WAN and Edge ATM switches. transfer (1995 issue), and intrinsic jitter adapted for packet transfer). LAN switches and hubs. criteria. Provides support functions for 1+1 Packet switches and hubs. APS operation. Network Interface Cards and Uplinks. Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. BLOCK DIAGRAM Section/ Line DCC Insertion Tx POS Frame Processor Tx Tx Tx Section O/H Line O/H Path O/H Processor Processor Processor Tx ATM Cell UTOPIA Level 1 Processor 8-bit x 52 MHz 155.52 Mbit/s WAN Section Path UTOPIA Level 2 Synch. Trace Buffer Trace Buffer 2 POS-PHY Level 16-bit x 52 MHz Rx ATM Cell Processor Rx Rx Rx Section O/H Line O/H Path O/H Processor Processor Processor Rx POS Frame Processor Section/ Sync Status, Line DCC BERM Extraction External APS JTAG Test Interface Microprocessor Interface Access Port Test Data 16-bit Microprocessor Bus PMC-2011690 (R2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS INTERNAL USE Copyright PMC-Sierra, Inc. 2002Released PM5384 S/UNI 1x155 Single Channel OC-3c ATM and POS Physical Layer Device TYPICAL APPLICATIONS TYPICAL STS-3C/STM-1 PACKET-OVER-SONET/SDH TYPICAL STS-3C/STM-1 ATM SWITCH PORT POS-PHY Level 2 Interface Link Layer PM5384 Device S/UNI 1x155 UTOPIA Level 2 Interface TFCLK TFCLK ATM Layer PM5384 TENB TENB Device S/UNI 1x155 TPRTY TPRTY TFCLK TFCLK TDAT 15:0 TDAT 15:0 TENB TENB TMOD TMOD TADR 4:0 TADR 4:0 TSOP TSOP TCA TCA RXD+/- TEOP TEOP Optical TSOC SD TSOC RXD+/- Transceiver TERR TERR Optical TPRTY TPRTY TXD+/- SD TADR 4:0 TADR 4:0 Transceiver TXD+/- TDAT 15:0 TDAT 15:0 PTPA PTPA RFCLK RFCLK STPA STPA RENB RENB RFCLK RADR 4:0 RADR 4:0 RFCLK RENB RENB RCA RCA RVAL RVAL RSOC RSOC RPRTY RPRTY RPRTY RPRTY RDAT 15:0 RDAT 15:0 RDAT 15:0 RDAT 15:0 RSOP RSOP REOP REOP RERR RERR JITTER PLOT Framed Jitter Tolerance at Nominal Voltage and Temperature with 1dB Optical Penalty 100 10 1 0.1 10 100 1000 10000 100000 1000000 10000000 Frequency (Hz) Head Office: To order documentation, All product documentation is available PMC-2011690 (R2) PMC-Sierra, Inc. send email to: on our web site at: Copyright PMC-Sierra, 8555 Baxter Place document pmc-sierra.com