512 Kbit SPI Serial Flash SST25VF512 A Microchip Technology Company Data Sheet SST serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25VF512 SPI serial flash memory is manufactured with SST s proprietary, high-performance CMOS SuperFlash technology. The split- gate cell design and thick-oxide tunneling injector attain better reliability and man- ufacturability compared with alternate approaches. Features Single 2.7-3.6V Read and Write Operations End-of-Write Detection Software Status Serial Interface Architecture Hold Pin (HOLD ) SPI Compatible: Mode 0 and Mode 3 Suspends a serial sequence to the memory 20 MHz Max Clock Frequency without deselecting the device Superior Reliability Write Protection (WP ) Endurance: 100,000 Cycles (typical) Enables/Disables the Lock-Down function of the status Greater than 100 years Data Retention register Low Power Consumption: Software Write Protection Active Read Current: 7 mA (typical) Write protection through Block-Protection bits in status Standby Current: 8 A (typical) register Flexible Erase Capability Packages Available Uniform 4 KByte sectors 8-lead SOIC (4.9mm x 6mm) Uniform 32 KByte overlay blocks 8-contact WSON Fast Erase and Byte-Program: Allnon-Pb(lead-free)devicesareRoHScompliant Chip-Erase Time: 70 ms (typical) Sector- or Block-Erase Time: 18 ms (typical) Byte-Program Time: 14 s (typical) Auto Address Increment (AAI) Programming Decrease total chip programming time over Byte-Pro- gram operations 2011 Silicon Storage Technology, Inc. www.microchip.com DS25076A 10/11512 Kbit SPI Serial Flash SST25VF512 A Microchip Technology Company Data Sheet Product Description SSTs serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25VF512 SPI serial flash memory is manufactured with SSTs proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and man- ufacturability compared with alternate approaches. The SST25VF512 device significantly improves performance, while lowering power consumption. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF512 device operates with a single 2.7-3.6V power supply. The SST25VF512 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pin assignments. 2011 Silicon Storage Technology, Inc. DS25076A 10/11 2