1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories Data Sheet FEATURES: Organized as 128K x8 / 256K x8 / 512K x8 Fast Erase and Byte-Program Single 4.5-5.5V Read and Write Operations Sector-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) Superior Reliability Byte-Program Time: 14 s (typical) Endurance: 100,000 Cycles (typical) Chip Rewrite Time: Greater than 100 years Data Retention 2 seconds (typical) for SST39SF010A Low Power Consumption 4 seconds (typical) for SST39SF020A (typical values at 14 MHz) 8 seconds (typical) for SST39SF040 Active Current: 10 mA (typical) End-of-Write Detection Standby Current: 30 A (typical) Toggle Bit Sector-Erase Capability Data Polling Uniform 4 KByte sectors TTL I/O Compatibility Fast Read Access Time: JEDEC Standard 55 ns Flash EEPROM Pinouts and command sets 70 ns Packages Available Latched Address and Data 32-lead PLCC Automatic Write Timing 32-lead TSOP (8mm x 14mm) 32-pin PDIP Internal V Generation PP All devices are RoHS compliant All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39SF010A/020A/040 are CMOS Multi-Purpose function of the applied voltage, current, and time of applica- Flash (MPF) manufactured with SSTs proprietary, high tion. Since for any given voltage range, the SuperFlash performance CMOS SuperFlash technology. The split-gate technology uses less current to program and has a shorter cell design and thick oxide tunneling injector attain better erase time, the total energy consumed during any Erase or reliability and manufacturability compared with alternate Program operation is less than alternative flash technolo- approaches. The SST39SF010A/020A/040 devices write gies. These devices also improve flexibility while lowering (Program or Erase) with a 4.5-5.5V power supply. The the cost for program, data, and configuration storage appli- SST39SF010A/020A/040 devices conform to JEDEC stan- cations. dard pinouts for x8 memories. The SuperFlash technology provides fixed Erase and Pro- Featuring high performance Byte-Program, the gram times, independent of the number of Erase/Program SST39SF010A/020A/040 devices provide a maximum cycles that have occurred. Therefore the system software Byte-Program time of 20 sec. These devices use Toggle or hardware does not have to be modified or de-rated as is Bit or Data Polling to indicate the completion of Program necessary with alternative flash technologies, whose Erase operation. To protect against inadvertent write, they have and Program times increase with accumulated Erase/Pro- on-chip hardware and Software Data Protection schemes. gram cycles. Designed, manufactured, and tested for a wide spectrum of To meet high density, surface mount requirements, the applications, these devices are offered with a guaranteed SST39SF010A/020A/040 are offered in 32-lead PLCC and typical endurance of 100,000 cycles. Data retention is rated 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also at greater than 100 years. available. See Figures 2, 3, and 4 for pin assignments. The SST39SF010A/020A/040 devices are suited for appli- cations that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inher- ently use less energy during erase and program than alter- native flash technologies. The total energy consumed is a 2010 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71147-09-000 01/10 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Device Operation Commands are used to initiate the memory operation func- is latched on the rising edge of the sixth WE pulse. The tions of the device. Commands are written to the device internal Erase operation begins after the sixth WE pulse. using standard microprocessor write sequences. A com- The End-of-Erase can be determined using either Data mand is written by asserting WE low while keeping CE Polling or Toggle Bit methods. See Figure 10 for timing low. The address bus is latched on the falling edge of WE waveforms. Any commands written during the Sector- or CE , whichever occurs last. The data bus is latched on Erase operation will be ignored. the rising edge of WE or CE , whichever occurs first. Chip-Erase Operation Read The SST39SF010A/020A/040 provide Chip-Erase opera- The Read operation of the SST39SF010A/020A/040 is tion, which allows the user to erase the entire memory controlled by CE and OE , both have to be low for the array to the 1s state. This is useful when the entire device system to obtain data from the outputs. CE is used for must be quickly erased. device selection. When CE is high, the chip is dese- The Chip-Erase operation is initiated by executing a six- lected and only standby power is consumed. OE is the byte Software Data Protection command sequence with output control and is used to gate data from the output Chip-Erase command (10H) with address 5555H in the last pins. The data bus is in high impedance state when byte sequence. The internal Erase operation begins with either CE or OE is high. Refer to the Read cycle timing the rising edge of the sixth WE or CE , whichever occurs diagram (Figure 5) for further details. first. During the internal Erase operation, the only valid read is Toggle Bit or Data Polling. See Table 4 for the command Byte-Program Operation sequence, Figure 11 for timing diagram, and Figure 19 for the flowchart. Any commands written during the Chip- The SST39SF010A/020A/040 are programmed on a byte- Erase operation will be ignored. by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte Write Operation Status Detection load sequence for Software Data Protection. The second The SST39SF010A/020A/040 provide two software means step is to load byte address and byte data. During the Byte- to detect the completion of a Write (Program or Erase) Program operation, the addresses are latched on the falling cycle, in order to optimize the system Write cycle time. The edge of either CE or WE , whichever occurs last. The software detection includes two status bits: Data Polling data is latched on the rising edge of either CE or WE , (DQ ) and Toggle Bit (DQ ). The End-of-Write detection 7 6 whichever occurs first. The third step is the internal Pro- mode is enabled after the rising edge of WE which ini- gram operation which is initiated after the rising edge of the tiates the internal Program or Erase operation. fourth WE or CE , whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. The actual completion of the nonvolatile write is asynchro- See Figures 6 and 7 for WE and CE controlled Program nous with the system therefore, either a Data Polling or operation timing diagrams and Figure 16 for flowcharts. Toggle Bit read may be simultaneous with the completion During the Program operation, the only valid reads are of the Write cycle. If this occurs, the system may possibly Data Polling and Toggle Bit. During the internal Program get an erroneous result, i.e., valid data may appear to con- operation, the host is free to perform additional tasks. Any flict with either DQ or DQ . In order to prevent spurious 7 6 commands written during the internal Program operation rejection, if an erroneous result occurs, the software routine will be ignored. should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- Sector-Erase Operation tion is valid. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector- Erase operation is initiated by executing a six-byte com- mand load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the fall- ing edge of the sixth WE pulse, while the command (30H) 2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 2