SST39VF3201C/SST39VF3202C 32-Mbit (x16) Multi-Purpose Flash Plus The SST39VF3201C and SST39VF3202C devices are 2M x16, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF3201C and SST39VF3202C write (Program or Erase) with a 2.7V-3.6V power supply. This device conforms to JEDEC standard pinouts for x16 memories. Fast Erase and Word-Program: Features - Sector-Erase Time: 18 ms (typical) Organized as 2M x16 - Block-Erase Time: 18 ms (typical) Single Voltage Read and Write Operations: - Chip-Erase Time: 35 ms (typical) - 2.7V-3.6V - Word-Program Time: 7 s (typical) Superior Reliability: Automatic Write Timing: - Endurance: 100,000 Cycles (Typical) - Internal V Generation PP - Greater than 100 years Data Retention End-of-Write Detection: Low-Power Consumption (typical values at - Toggle Bits 5 MHz): - Data Polling - Active Current: 6 mA (typical) - RY/BY Pin - Standby Current: 4 A (typical) CMOS I/O Compatibility - Auto Low-Power Mode: 4 A (typical) JEDEC Standard: Hardware Block Protection/WP Input Pin: - Flash EEPROM Pin Assignments - Top Block Protection (top two 4-KWord Packages Available: blocks) for SST39VF3202C - 48-lead TSOP (12 mm x 20 mm) - Bottom Block-Protection (bottom two 4- - 48-ball TFBGA (6 mm x 8 mm) KWord blocks) for SST39VF3201C All devices are RoHS compliant Sector-Erase Capability: - Uniform 2 KWord sectors Packages Block-Erase Capability: - 48-lead TSOP (12 mm x 20 mm) - Flexible block architecture - 48-ball TFBGA (6 mm x 8 mm) - Eight 4-KWord blocks, 63 32-KWord blocks Chip-Erase Capability Erase-Suspend/Erase-Resume Capabilities Hardware Reset Pin (RST ) Security-ID Feature: - Microchip: 128 bits User: 128 words Fast Read Access Time: - 70 ns Latched Address and Data 2009-2020 Microchip Technology Inc. DS20005020C-page 1SST39VF3201C/SST39VF3202C DESCRIPTION The SST39VF3201C and SST39VF3202C devices are 2M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF3201C/ SST39VF3202C write (Program or Erase) with a 2.7V-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high-performance Word Program, the SST39VF3201C/SST39VF3202C devices provide a typical Word Pro- gram time of 7 sec. These devices use Toggle Bit, Data Polling or RY/BY pin to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured and tested for a wide spectrum of applications, these devices are offered with a typical endur- ance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF3201C/SST39VF3202C devices are suited for applications that require convenient and economical updat- ing of program, configuration or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alterna- tive Flash technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative Flash technologies. These devices also improve flexibility while lowering the cost for program, data and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or derated as is necessary with alternative Flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. To meet high-density, surface mount requirements, the SST39VF3201C/SST39VF3202C devices are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figure 2 and Figure 3 for pin assignments. BLOCK DIAGRAM FIGURE 1: FUNCTIONAL BLOCK DIAGRAM SuperFlash X-Decoder Memory Memory Address Address Buffer & Latches Y-Decoder CE OE WE Control Logic WP RESET I/O Buffers and Data Latches RY/BY DQ - DQ 15 0 2009-2020 Microchip Technology Inc. DS20005020C-page 2