4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C/SST39VF402C/SST39LF401C/SST39LF402C Data Sheet SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 256K x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high per- formance CMOS SuperFlash technology. The split-gate cell design and thick- oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. SST39LF401C/402C write (Program or Erase) with a 3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pinouts for x16 memories. Features Organized as 256K x16 Security-ID Feature 128 bits User: 128 words SingleVoltage Read andWrite Operations Fast Read AccessTime: 2.7-3.6V for SST39VF401C/402C 3.0-3.6V for SST39LF401C/402C 70 ns for SST39VF401C/402C 55 ns for SST39LF401C/402C Superior Reliability Fast Erase andWord-Program: Endurance: 100,000 Cycles (Typical) Greater than 100 years Data Retention Sector-EraseTime: 18 ms (typical) Block-EraseTime: 18 ms (typical) Low Power Consumption (typical values at 5 MHz) Chip-EraseTime: 40 ms (typical) Word-ProgramTime: 7 s (typical) Active Current: 5 mA (typical) Standby Current: 3 A (typical) AutomaticWriteTiming Auto Low Power Mode: 3 A (typical) InternalV Generation PP Hardware Block-Protection/WP Input Pin End-of-Write Detection Top Block-Protection (top 8 KWord) Bottom Block-Protection (bottom 8 KWord) Toggle Bits Data Polling Sector-Erase Capability Ready/Busy Pin Uniform 2 KWord sectors CMOS I/O Compatibility Block-Erase Capability JEDEC Standard Flexible block architecture one 8-, two 4-, one 16-, and seven 32-KWord blocks Flash EEPROM Pinouts and command sets Chip-Erase Capability Packages Available 48-leadTSOP (12mm x 20mm) Erase-Suspend/Erase-Resume Capabilities 48-ballTFBGA (6mm x 8mm) 48-ball WFBGA (4mm x 6mm) Hardware Reset Pin (RST ) AlldevicesareRoHScompliant Latched Address and Data 2014 Silicon Storage Technology, Inc. www.microchip.com DS20005053B 04/144 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C/SST39VF402C/SST39LF401C/SST39LF402C Data Sheet Product Description The SST39VF401C/402C and SST39LF401C/402C devices are 256K x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. SST39LF401C/402C write (Program or Erase) with a 3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39VF401C/402C and SST39LF401C/402C devices provide a typical Word-Program time of 7 sec. These devices use Toggle Bit, Data Polling, or the RY/BY pin to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF401C/402C and SST39LF401C/402C devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system appli- cations, they significantly improve performance and reliability, while lowering power consumption.They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.These devices also improve flexibility while lowering the cost for program, data, and con- figuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro- gram times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF401C/402C and SST39LF401C/402C are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4 for pin assignments. 2014 Silicon Storage Technology, Inc. DS20005053B 04/14 2