8 Mbit LPC Flash SST49LF080A SST49LF080A8 Mbit LPC Flash Data Sheet FEATURES: LPC Interface Flash Two Operational Modes SST49LF080A: 1024K x8 (8 Mbit) Low Pin Count (LPC) Interface mode for in-system operation Conforms to Intel LPC Interface Specification 1.0 Parallel Programming (PP) Mode for fast production Flexible Erase Capability programming Uniform 4 KByte Sectors LPC Interface Mode Uniform 64 KByte overlay blocks 5-signal communication interface supporting 64 KByte Top Boot Block protection byte Read and Write Chip-Erase for PP Mode Only 33 MHz clock frequency operation Single 3.0-3.6V Read and Write Operations WP and TBL pins provide hardware write protect Superior Reliability for entire chip and/or top boot block Standard SDP Command Set Endurance: 100,000 Cycles (typical) Data Polling and Toggle Bit for End-of-Write Greater than 100 years Data Retention detection Low Power Consumption 5 GPI pins for system design flexibility Active Read Current: 6 mA (typical) 4 ID pins for multi-chip selection Standby Current: 10 A (typical) Parallel Programming (PP) Mode Fast Sector-Erase/Byte-Program Operation 11-pin multiplexed address and 8-pin data Sector-Erase Time: 18 ms (typical) I/O interface Block-Erase Time: 18 ms (typical) Supports fast programming In-System on Chip-Erase Time: 70 ms (typical) programmer equipment Byte-Program Time: 14 s (typical) CMOS and PCI I/O Compatibility Chip Rewrite Time: 16 seconds (typical) Packages Available Single-pulse Program or Erase Internal timing generation 32-lead PLCC 32-lead TSOP (8mm x 14mm) All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST49LF080A flash memory device is designed to has a shorter erase time the total energy consumed during interface with the LPC bus for PC and Internet Appliance any Erase or Program operation is less than alternative application in compliance with Intel Low Pin Count (LPC) flash memory technologies. The SST49LF080A product Interface Specification 1.0. Two interface modes are sup- provides a maximum Byte-Program time of 20 sec. The ported: LPC mode for in-system operations and Parallel entire memory can be erased and programmed byte-by- Programming (PP) mode to interface with programming byte typically in 16 seconds when using status detection equipment. features such as Toggle Bit or Data Polling to indicate the completion of Program operation. The SuperFlash technol- The SST49LF080A flash memory device is manufactured ogy provides fixed Erase and Program time, independent with SSTs proprietary, high-performance SuperFlash of the number of Erase/Program cycles that have per- Technology. The split-gate cell design and thick-oxide tun- formed. Therefore the system software or hardware does neling injector attain better reliability and manufacturability not have to be calibrated or correlated to the cumulative compared with alternate approaches. The SST49LF080A number of Erase cycles as is necessary with alternative device significantly improves performance and reliability, flash memory technologies, whose Erase and Program while lowering power consumption. The SST49LF080A time increase with accumulated Erase/Program cycles. device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Pro- To meet high density, surface mount requirements, the gram than alternative flash memory technologies. The total SST49LF080A device is offered in 32-lead TSOP and 32- energy consumed is a function of the applied voltage, cur- lead PLCC packages. See Figures 2 and 3 for pin assign- rent and time of application. For any give voltage range, the ments and Table 1 for pin descriptions. SuperFlash technology uses less current to program and 2006 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71235-02-000 5/06 Intel is a registered trademark of Intel Corporation. 1 These specifications are subject to change without notice.8 Mbit LPC Flash SST49LF080A Data Sheet TABLE OF CONTENTS PRODUCT DESCRIPTION . 1 LIST OF FIGURES . 4 LIST OF TABLES . 5 FUNCTIONAL BLOCK DIAGRAM 6 PIN ASSIGNMENTS 7 DEVICE MEMORY MAPS 9 DESIGN CONSIDERATIONS 10 PRODUCT IDENTIFICATION 10 MODE SELECTION 10 LPC MODE 10 Device Operation . 10 CE 11 LFRAME . 11 TBL , WP 11 INIT , RST . 11 System Memory Mapping . 11 Response To Invalid Fields 14 Abort Mechanism . 14 Write Operation Status Detection . 14 Data Polling . 14 Toggle Bit 14 Multiple Device Selection . 15 Registers 15 General Purpose Inputs Register . 16 JEDEC ID Registers . 16 PARALLEL PROGRAMMING MODE 17 Device Operation . 17 Reset . 17 Read . 17 Byte-Program Operation 17 Sector-Erase Operation 17 Block-Erase Operation . 17 Chip-Erase Operation 17 2006 Silicon Storage Technology, Inc. S71235-02-000 5/06 2