ECL Pro 3.3V/5V PECL/ECL 3GHz Micrel, Inc. SY100EP56V ECL Pro DUAL DIFFERENTIAL SY100EP56V 2:1 MULTIPLEXER FEATURES Dual, fully differential 2:1 PECL/ECL multiplexer Guaranteed AC parameters over temperature/ ECL Pro voltage: > 3GHz f (toggle) MAX < 100ps within device skew DESCRIPTION < 230ps rise/fall times < 500ps propagation delay The SY100EP56V is a high-speed, low-skew, fully differential Dual PECL/ECL 2:1 multiplexer. This device is a Flexible power supply: 3.0V to 5.5V pin-for-pin, plug-in replacement to the MC10/100EP56DT. Wide operating temperature range: 40C to +85C Two separate 2:1 multiplexers (Channel 0 and Channel 1) V reference for AC-coupled and single-ended BB with dedicated select control pins (SEL0 and SEL1) are applications implemented in a 20-pin TSSOP package. The signal-path Both channels have independent input select or inputs (D0a, D0b and D1a, D1b) accept differential signals common select control as low as 150mV pk-pk. For applications that require common select control for both channels A & B, a common 100k PECL/ECL compatible logic select pin (COM SEL) is available. All I/O pins are 100k Available in 20-pin TSSOP package PECL/ECL logic compatible. ACperformance is guaranteed over the industrial 40C to +85C temperature range and 3.0V to 5.5V supply voltage range. This device will operate in PECL/LVPECL or ECL/ CROSS REFERENCE TABLE LVECL mode. The 500ps max (400 typ) propagation delay is matched for all signal and logic select paths: D-to-Q , OUT SEL-to-Q , and COM SEL-to-Q . Two V output Micrel Semiconductor ON Semiconductor OUT OUT BB reference pins (approx equal to V 1.4V) are available CC SY100EP56VK4I MC100EP56DT for ACcoupled or single-ended applications. SY100EP56VK4ITR MC100EP56DTR2 The SY100EP56V is part of Micrels high-speed, Precision Edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low skew fanout buffers, translators, and clock dividers. MUX SELECT TRUTH TABLE SEL0 SEL1 COM SEL Q0, /Q0 Q1, /Q1 XX H a a LL Lb b LH L b a HH L a a HL L a b ECL Pro is a trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-120505 1 Issue Date: December 2005 hbwhelp micrel.com or (408) 955-1690ECL Pro Micrel, Inc. SY100EP56V PACKAGE/ORDERING INFORMATION (1) Ordering Information D0a 1 20 VCC 1 Package Operating Package Lead /D0a 2 19 Q0 Part Number Type Range Marking Finish VBB0 3 18 /Q0 SY100EP56VK4I K4-20-1 Industrial XEP56V Sn-Pb 0 4 17 SEL0 D0b (2) SY100EP56VK4ITR K4-20-1 Industrial XEP56V Sn-Pb /D0b 5 16 COM SEL (3) SY100EP56VK4G K4-20-1 Industrial XEP56V with Pb-Free Pb-Free bar-line indicator NiPdAu SEL1 D1a 6 15 (2, 3) 1 SY100EP56VK4GTR K4-20-1 Industrial XEP56V with Pb-Free /D1a 7 14 VCC Pb-Free bar-line indicator NiPdAu 8 13 VBB1 Q1 Notes: 0 D1b 9 12 /Q1 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. /D1b 10 11 VEE 3. Pb-Free package is recommended for new designs. 20-Pin TSSOP (K4-20-1) PIN DESCRIPTION Pin Pin Number Function D0a, /D0a 1, 2, Channel 0 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is D0b, /D0b 4, 5 controlled by SEL0, or COM SEL. The signal inputs include internal 75k pull-down resistors. Default condition is LOW when left floating. The input signal should be terminated externally. See Termination section D1a, /D1a 6, 7 Channel 1 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is D1b, /D1b 9, 10 controlled by SEL1, or COM SEL. The signal inputs include internal 75k pull-down resistors. Default condition is a logic LOW when left floating. The input signal should be terminated externally. See Termination section VBB0, VBB1 3, 8 Channel 0 and Channel 1 reference output voltage. This reference is typically used to bias the unused inverting input for single-ended input applications, or as the termination point for AC coupled differential input applications. V reference value is approximately V 1.4V, and tracks BB CC V 1:1. Maximum sink/source capability is 0.50mA. For single ended PECL inputs, connect to CC the unused input through a 50 resistor. Decouple the V pin with a 0.01F capacitor. For PECL/ BB LVPECL inputs, the decoupling capacitor is connected to V , since PECL signals are referenced CC to V . Leave floating if not used. CC VEE 11 Negative Power Supply: For PECL/LVPECL applications, connect to GND. /Q1, Q1 12, 13 Channel 1 100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50 resistor to V 2V. Unused output pairs may be left floating. Unused single-ended outputs must CC have a balanced load. For AC-coupled applications, the output stage emitter follower must have a DC current path to ground. See Termination section. SEL1, SEL0 15, 17 100KEP PECL/ECL compatible Channel 1 and Channel 0 MUX select control. See MUX Select Truth Table. Each pin includes an internal 75k pull-down resistor. Default condition when left floating is LOW. COM SEL 16 100KEP PECL/ECL compatible Channel 1 and Channel 0 Common MUX select control. This is the common select control pin for both Channels 0 and 1. Includes an internal 75k pull-down resistor. Default condition when left floating is LOW. Leave floating when not used. /Q0, Q0 18, 19 Channel 0 100K EP PECL/ECL compatible differential output. PECL/ECL termination is with a 50 resistor to V 2V. Unused output pairs may be left floating. Unused single-ended outputs CC must have a balanced load. For ACcoupled applications, the output stage emitter follower must have a DC current path to ground. See Termination section. VCC 14, 20 Positive Power Supply: Both V pins must be connected to the same power supply externally. CC Bypass with 0.1F//0.01F low ESR capacitors. M9999-120505 2 hbwhelp micrel.com or (408) 955-1690