Precision Edge SY58025U Micrel, Inc. Precision Edge ULTRA PRECISION DUAL 2:1 CML SY58025U MUX WITH INTERNAL I/O TERMINATION FEATURES Two independent differential 2:1 multiplexers Guaranteed AC performance over temperature and Precision Edge voltage: DC-to >10.7Gbps data rate throughput DESCRIPTION <290ps IN-to-Out t pd <70ps t /t times r f The SY58025U features two ultra-fast, low jitter 2:1 Unique, patent-pending input isolation design differential muxes with a guaranteed maximum data or clock minimizes crosstalk throughput of 10.7Gbps or 7GHz, respectively. Ultra-low jitter design: The SY58025U differential inputs include a unique, <1ps random jitter RMS internal termination design that allows access to the <10ps deterministic jitter PP termination network through a VT pin. The device easily <10ps total jitter (clock) PP interfaces to different logic standards, both AC- and DC- <0.7ps crosstalk-induced jitter RMS coupled, without external resistor-bias and termination Unique, patent-pending 50 input termination and networks. The result is a clean, stub-free, low jitter interface VT pin accepts DC-coupled and AC-coupled inputs solution. The differential CML output is optimized for 50 (CML, LVDS, PECL) environments with internal 50 source termination and a 400mV output swing. Typical 400mV CML output swing (R = 50) L The SY58025U operates from a 2.5V or 3.3V supply and Internal 50 input termination is guaranteed over the full industrial temperature range Power supply 2.5V 5% or 3.3V 10% (40C to +85C). The SY58025U is part of Micrels Precision 40C to +85C temperature range Edge product family. Available in 32-pin (5mm 5mm) MLF package All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS Data communication systems All SONET OC3-OC-768 applications All Fibre Channel applications All GigE applications FUNCTIONAL BLOCK DIAGRAM INA0 INB0 50 50 V 0 V 0 TA0 TB0 50 50 /INA0 /INB0 QA QB V V REF-ACA0 REF-ACB0 MUX A MUX B /QA /QB INA1 INB1 50 50 S S V 1 V 1 TA1 TB1 50 50 /INA1 /INB1 V V REF-ACA1 REF-ACB1 SELA SELB (TTL/CMOS) (TTL/CMOS) United States Patent No. RE44,134 AnyGate and Precision Edge are registered trademarks of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-082707 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge SY58025U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 32 31 30 29 28 27 26 25 SY58025UMI MLF-32 Industrial SY58025U Sn-Pb 1 24 INB0 GND (2) 23 SY58025UMITR MLF-32 Industrial SY58025U Sn-Pb VTB0 2 VCC VREF-ACB0 3 22 QA (3) SY58025UMG MLF-32 Industrial SY58025Uwith Pb-Free /INB0 4 21 /QA Pb-Free bar-line indicator NiPdAu 5 20 INB1 VCC 6 19 VTB1 NC (2, 3) SY58025UMGTR MLF-32 Industrial SY58025U with Pb-Free VREF-ACB1 7 18 SELA Pb-Free bar-line indicator NiPdAu /INB1 8 17 VCC 910 111213141516 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 32-Pin MLF (MLF-32) PIN DESCRIPTION Pin Number Pin Name Pin Function 25, 28, INA0, /INA0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 29, 32, INA1, /INA1, accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair 1, 4, INB0, /INB0, internally terminates to a V pin through 50. Note that these inputs will default to an T 5, 8 INB1, /INB1 indeterminate state if left open. Unused differential input pairs can be terminated by and the complementary input to GND through a 1k resistor. connecting one input to V CC The VT pin is to be left open in this configuration. Please refer to the Input Interface Applications section for more details. 26, 30, 2, 6 VTA0 , VTA1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT VTB0, VTB1 pin. Each V pin provides a center-tap to a termination network for maximum interface T flexibility. See Input Interface Applications section for more details. 18, 15 SELA, SELB Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs select the inputs to the multiplexers. These inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is V /2. CC 27, 31, 3, 7 VREF-ACA0, Reference Output Voltage: These outputs bias to V 1.2V. Connect to the VT pin when CC VREF-ACA1, AC-coupling the data inputs. Bypass with 0.01F low ESR capacitor to V . Maximum CC VREF-ACB0, current source or sink is 0.5mA. See Input Interface Applications section. VREF-ACB1 10, 13, 16, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors. 17, 20, 23 22, 21, QA, /QA, Differential CML Outputs: MUX A and MUX B selected CML outputs. See Output 12, 11 QB, /QB Interface Applications section for termination. Refer to the Truth Table for logic operation. 9, 24 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed pad 14, 19 NC Not connected. M9999-082707 2 hbwhelp micrel.com or (408) 955-1690 INA1 GND VCC VREF-ACA1 /QB VTA1 QB INA1 VCC /INA0 NC VREF-ACA0 SELB VTA0 INA0 VCC