SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully Precision Edge differential CML 2:1 MUX capable of processing clock Features signals up to 2.5GHz and data patterns up to 4.25Gbps. The SY58609U is optimized to provide a buffered output Precision 400mV CML 2:1 MUX of the selected input with less than 20ps of skew and Guaranteed AC performance over temperature and less than 10ps total jitter. pp voltage: The differential input includes Micrels unique, 3-pin DC-to > 4.25Gbps throughput input termination architecture that interfaces to LVPECL, <370ps propagation delay (IN-to-Q) LVDS or CML differential signals, (AC- or DC-coupled) <90ps rise/fall times as small as 100mV (200mV ) without any level-shifting pp Fail Safe Input or termination resistor networks in the signal path. For Prevents outputs from oscillating when input is AC-coupled input interface applications, an integrated invalid reference voltage (V ) is provided to bias the V pin. REF-AC T The outputs are 400mV CML, with extremely fast Unique, patented MUX input isolation design rise/fall times guaranteed to be less than 90ps. minimizes adjacent channel crosstalk The SY58609U operates from a 2.5V 5% supply or Ultra-low jitter design 3.3V 10% supply and is guaranteed over the full <1ps cycle-to-cycle jitter RMS industrial temperature range (40C to +85C). For <10ps total jitter PP applications that require LVPECL or LVDS outputs, <1ps random jitter RMS consider Micrels SY58610U and SY58611U, 2:1 MUX <10ps deterministic jitter with 800mV and 325mV output swings, respectively. PP The SY58609U is part of Micrels high-speed, Precision High-speed CML outputs Edge product line. 2.5V 5% or 3.3V 10% power supply operation Datasheets and support documentation can be found on Industrial temperature range: 40C to +85C Micrels web site at: www.micrel.com. Available in 16-pin (3mm x 3mm) QFN package Applications Functional Block Diagram Data Distribution: OC-48, OC-48+FEC, XAUI SONET clock and data distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution Markets Storage ATE Test and measurement Enterprise networking equipment High-end servers Access United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY58609U (1) Ordering Information Part Number Package Operating Package Marking Lead Finish Type Range SY58609UMG QFN-16 Industrial 609U with Pb-Free NiPdAu bar-line indicator Pb-Free (2) SY58609UMGTR QFN-16 Industrial 609U with Pb-Free NiPdAu bar-line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. Pin Configuration Truth Table SEL Output 0 IN0 Selected 1 IN1 Selected 16-Pin QFN Pin Description Pin Number Pin Name Pin Function 1, 4 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications subsection. 2, 3 VREF-AC0, Reference Voltage: These outputs bias to V 1.2V. They are used for AC-coupling inputs CC VREF-AC1 IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See Input Interface Applications subsection. 5, 6 IN1, /IN1 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of the pairs 15, 16 IN0, /IN0 internally terminates with 50 to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See Input Interface Applications subsection. 7 SEL Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is V /2. CC 8, 13 VCC Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the V CC pins as possible. 9, 12 /Q, Q CML Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 400mV. Normally terminate with 100 across Q and /Q. Unused output pair may be left floating with no impact on jitter. See CML Output Termination subsection. 10, 11 GND Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins. 14 NC No connect. August 2007 2 M9999-082907-C hbwhelp micrel.com or (408) 955-1690