ClockWorks 5V/3.3V DUAL SY89420V PHASE LOCKED LOOP FINAL FEATURES DESCRIPTION 3.3V and 5V power supply options The SY89420V device consists of two identical, low jitter, digital Phase Locked Loops based on Micrel-Synergy s 1.12GHz maximum VCO frequency differential PLL technology. Each of the PLLs (PLLA and 30MHz to 560MHz reference input operating PLLB) is capable of operating in the 30MHz to 560MHz frequency input reference frequency range independently of the other Frequency doubler mode and is configurable separately. The PLLs can be configured Low jitter design to be matched in all regards, or can be configured so that PLLB is used as a frequency doubler, while PLLA is used PECL differential outputs to regenerate the undoubled frequency. PECL and TTL reference voltages available Two reference inputs (RINX and RINX), two feedback External loop filter optimizes performance/cost inputs (FINX and FINX), two filter pins (F1X and F2X) and Available in 28-pin PLCC package two differential outputs (FOUTX and FOUTX) are provided for each of the two PLLs. The reference and feedback inputs can be used as either differential or single-ended inputs. In single-ended mode RINX and FINX can be APPLICATIONS connected to either VBB for normal 100K PECL levels or VTH for normal TTL levels. Workstations Feedback for the loops is realized by connecting FOUTX, Advanced communications FOUTX to FINX, FINX by means of external circuitry. This allows the user the flexibility of inserting additional circuitry High-end consumer off-chip in the feedback paths, such as a divider. Pulldown High-performance computing resistors are required for the FOUTX and FOUTX pins. Use of a phase-frequency detector results in excellent PLL locking and tracking characteristics. Error correction PIN CONFIGURATION voltages are generated by the detector if either phase or frequency deviations occur. The VCO has a frequency range covering more than a 2:1 ratio from 480MHz to 1120MHz. Select pins S1X and S2X are used to program the N dividers for optimum VCO operation, in other words with the VCO in the center of its range. Additional select pins, 25 24 23 22 21 20 19 VCCOB 26 S3B and S4B, are provided for PLLB. When both S3B and 18 S4B S4B are low, PLLB is identical to PLLA. When S3B is high, FOUTB 27 17 RINB NB can be set to 1, 10, 18, or 20. When S4B is high, the FOUTB 28 16 RINB TOP VIEW frequency doubler option is enabled (P = 2). All Select pins VCC 1 PLCC 15 VEE are TTL compatible. J28-1 FOUTA 2 14 RINA FOUTA 3 13 RINA VCCOA VBB 4 12 56789 1011 Rev.: K Amendment: /0 Issue Date: May 2000 1 S1A S1B S2A S2B F1A F1B F2A F2B VTH S3B FINA FINB FINA FINBClockWorks Micrel SY89420V BLOCK DIAGRAM F1A F2A LOOP RINA FILTER D RINA PHASE-FREQUENCY VCO DETECTOR FINA D S1A NA FINA (2, 4, 8, 16) S2A FOUTA FOUTA VBB VTH FOUTB FOUTB S1B NB S2B (1,2,4,8,10,12,16,20) RINB S3B D RINB PHASE-FREQUENCY VCO DETECTOR FINB P LOOP (1, 2) FINB FILTER S4B F1B F2B 2