NOT RECOMMENDED FOR NEW DESIGNS Precision Edge 3.3V, 500MHz, 1:9 DIFFERENTIAL Micrel, Inc. SY89808L Precision Edge HSTL (1.5V) FANOUT BUFFER/ SY89808L TRANSLATOR FEATURES 9 differential HSTL (1.5V compatible) output pairs Precision Edge 500MHz maximum clock frequency Triple-buffered enable function DESCRIPTION 3.3V core supply, 1.8V output supply for reduced power The SY89808L is a High-Performance Bus Clock Driver with LVPECL and HSTL inputs 9 differential HSTL (High-Speed Transceiver Logic) 1.5V compatible output pairs. The part is designed for use in low- HSTL outputs drive 50 to ground with no voltage (3.3V/1.8V) applications which require a large number offset voltage of outputs to drive precisely aligned, ultra-low skew signals to Low pin-to-pin skew (25ps max.) their destination. The input is multiplexed from either HSTL or Guaranteed over industrial 40C to +85C LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the temperature range CLK SEL pin. Available in 32-pin TQFP package The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can APPLICATIONS occur with an asynchronous control. The triple-buffering feature provides a three-clock delay from the time the OE input is Workstations asserted/de-asserted to when the clock appears at the outputs. Parallel processor-based systems The SY89808L features an ultra-low pin-to-pin skew of less High-performance computing than 25ps. The SY89808L is available in a 32-TQFP space Communications saving package, enabling a lower overall cost solution. TRUTH TABLE (1) OE CLK SEL Q Q /Q /Q 0 8 0 8 LOGIC SYMBOL 0 0 LOW HIGH 0 1 LOW HIGH CLK SEL 1 0 HSTL CLK /HSTL CLK HSTL CLK 1 1 LVPECL CLK /LVPECL CLK 0 /HSTL CLK 9 Notes: Q0 Q8 1. The OE (output enable) signal is synchronized with the low level of the 9 /Q0 /Q8 HSTL CLK and LVPECL CLK signal. LVPECL CLK 1 TYPICAL PERFORMANCE EN /LVPECL CLK ENABLE Output Amplitude LOGIC vs. Frequency OE 900 800 700 600 500 400 300 200 FREQUENCY (MHz) Precision Edge is a registered trademark of Micrel, Inc. Rev.: E Amendment: /0 M9999-091405 1 hbwhelp micrel.com or (408) 955-1690 Issue Date: September 2005 AMPLITUDE (mV) 0 200 400 600 800 1000 1200 1400 1600 Precision Edge Micrel, Inc. SY89808L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 32 31 30 29 28 27 26 25 VCCI 1 24 VCCO SY89808LTI T32-1 Industrial SY89808LTI Sn-Pb HSTL CLK 2 23 Q3 (2) SY89808LTITR T32-1 Industrial SY89808LTI Sn-Pb 3 /HSTL CLK 22 /Q3 (3) SY89808LTG T32-1 Industrial SY89808LTG with NiPdAu CLK SEL 21 Q4 4 Top View Pb-Free bar line indicator Pb-Free 5 20 /Q4 LVPECL CLK (2, 3) SY89808LTGTR T32-1 Industrial SY89808LTG with NiPdAu /LVPECL CLK 6 19 Q5 Pb-Free bar line indicator Pb-Free /Q5 GND 7 18 OE 8 17 VCCO Notes: 9 1011 12 131415 16 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 32-Pin TQFP (T32-1) PIN DESCRIPTION Pin Number Pin Name Type Pin Function 2, 3 HSTL CLK, HSTL Differential clock input selected by CLK SEL. Can be left floating if not /HSTL CLK Input selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50 to GND. 5, 6 LVPECL CLK, LVPECL Differential clock input selected by CLK SEL. Can be left floating. Floating /LVPECL CLK Input input, if selected produces a LOW at the output (internal 75 pull-downs). Requires external termination. 75k pull-up. 4 CLK SEL LVTTL Selects HSTL CLK input when LOW and LVPECL CLK output when HIGH. Input 11k pull-up. 8 OE LVTTL Enable input synchronized internally to prevent glitching of the Q0-Q8 and Input /Q0-/Q8 outputs. Must be a minimum of three clock periods wide if synchronous with the CLK inputs and must meet the t and t requirements S H (refer to AC Electrical Characteristics). If asynchronous, must be a minimum of four clock periods wide. 11k pull-up. 31, 29, 27, 23, Q0Q8 HSTL Differential clock outputs from HSTL CLK when CLK SEL = LOW and 21, 19, 15, 13, Output LVPECL outputs when CLK SEL = HIGH. HSTL outputs must be terminated 11 with 50 to GND. Q0Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. 30, 28, 26, 22, /Q0/Q8 HSTL Differential clock outputs from HSTL CLK when CLK SEL = LOW and 20, 18, 14, 12, Output LVPECL outputs when CLK SEL = HIGH. HSTL outputs must be terminated 10 with 50 to GND. /Q0/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. 1 VCCI VCC Core Core V connected to 3.3V supply. Bypass with 0.1 F in parallel with CC Power 0.01 F low ESR capacitors as close to V pin as possible. CCI 9, 16, 17, 24, VCCO VCC Output Output Buffer V connected to 1.8V supply. Bypass with 0.1 F in parallel CC 25, 32 Power with 0.01 F low ESR capacitors as close to V pins as possible. All V CCO CCO pins should be connected together on the PCB. 7 GND Ground Ground. M9999-091405 2 hbwhelp micrel.com or (408) 955-1690 VCCO VCCO Q0 /Q8 Q8 /Q0 Q1 /Q7 /Q1 Q7 Q2 /Q6 Q6 /Q2 VCCO VCCO