Precision Edge 2.5V/3.3V TWO INPUT, 1GHz LVTTL/CMOS- Micrel, Inc. SY89834U Precision Edge TO-LVPECL 1:4 FANOUT BUFFER/ SY89834U TRANSLATOR WITH 2:1 INPUT MUX FEATURES Selects between two LVTTL/CMOS inputs and Precision Edge provides 4 LVPECL output copies Guaranteed AC performance over temperature and voltage: DESCRIPTION DC-to >1.0GHz throughput <500ps propagation delay (IN-to-Q) The SY89834U is a high-speed, 1GHz LVTTL/CMOS-to- < 20ps within-device skew LVPECL fanout buffer/translator optimized for high-speed < 225ps rise/fall time ultra-low skew applications. The input stage is designed to accept two single-ended LVTTL/CMOS compatible signals Ultra-low jitter design: that feed into a 2:1 MUX. The selected input is translated < 1ps cycle-to-cycle jitter RMS and distributed as four differential 100K LVPECL outputs. < 1ps random jitter RMS Within device skew is guaranteed to be less than 20ps over < 10ps deterministic jitter PP supply voltage and temperature. < 10ps total jitter (clock) PP The single-ended input buffers accept TTL/CMOS logic Low voltage 2.5V and 3.3V supply operation levels. The internal threshold of the buffers is defined as 100K LVPECL outputs V /2 CC . Industrial temperature range: 40C to +85C The SY89834U is a part of Micrel s high-speed Precision Edge family. For applications that require a different I/O Includes a 2:1 MUX select input combination, consult Micrel s website at: www.micrel.com, Accepts single-ended TTL/CMOS inputs and and choose from a comprehensive product line of high- provides four LVPECL outputs speed, low-skew fanout buffers, translators and clock Available in 16-pin (3mm 3mm) MLF package generators. APPLICATIONS FUNCTIONAL BLOCK DIAGRAM Processor clock distribution/translation SONET clock distribution/translation 1:4 Fibre Channel clock distribution/translation Q0 Gigabit Ethernet clock distribution/translation /Q0 Single-ended ASIC-to-differential communication SEL (LVTTL/CMOS) IC signal translation Q1 IN1 /Q1 (LVTTL/CMOS) 1 MUX 0 IN2 Q2 (LVTTL/CMOS) /Q2 D Q EN LVTTL/CMOS) Q3 /Q3 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. August 2005 M9999-080505 1 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89834U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 16 15 14 13 Part Number Type Range Marking Finish Q1 1 12 IN1 SY89834UMI MLF-16 Industrial 834U Sn-Pb /Q1 2 11 SEL (2) SY89834UMITR MLF-16 Industrial 834U Sn-Pb 3 10 NC Q2 (3) SY89834UMG MLF-16 Industrial 834U with Pb-Free NiPdAu /Q2 4 9 IN2 bar line indicator Pb-Free 5 6 7 8 (2, 3) SY89834UMGTR MLF-16 Industrial 834U with Pb-Free NiPdAu bar line indicator Pb-Free Notes: 16-Pin MLF (MLF-16) 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 15, 16 Q0, /Q0 Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies 1, 2, Q1, /Q1 of the inputs. Please refer to the Truth Table section for details. Unused output pairs may be 3, 4, Q2, /Q2 left open. Terminate wtih 50 to V 2V. See Output Termination Recommendations section CC 5, 6 Q3, /Q3 for more details. 8 EN This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state (enabled) if left open. 12, IN1 Single-ended TTL/CMOS-compatible inputs to the device. These inputs are internally connected 9 IN2 to a 25k pull-up resistor and will default to logic HIGH state if left open. The input threshold is V /2. CC 10 NC No connect. Not internally connected. 11 SEL TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is V /2. HIGH at CC the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25k pull-up resistor. The default state is HIGH when left floating. 13 GND Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground. 7, 14 VCC Positive Power Supply: Bypass with 0.1 F//0.01 F low ESR capacitors and place as close to each VCC pin as possible. TRUTH TABLE IN1 IN2 EN SEL Q0Q3 /Q0Q3 0 X 110 1 1 X 111 0 X 0100 1 X 1101 0 (1) (1) XX 0 X 0 0 Note: 1. On next negative transition of the input signal (IN). M9999-080505 2 hbwhelp micrel.com or (408) 955-1690 Q3 /Q0 /Q3 Q0 VCC VCC EN GND