ZL40206 Precision 1:8 LVPECL Fanout Buffer Data Sheet March 2016 Ordering Information Features ZL40206LDG1 32 Pin QFN Trays Inputs/Outputs ZL40206LDF1 32 Pin QFN Tape and Reel Accepts differential or single-ended input Matte Tin LVPECL, LVDS, CML, HCSL, LVCMOS Package size: 5 x 5 mm Eight precision LVPECL outputs o o -40 C to +85 C Operating frequency up to 750 MHz Applications Power General purpose clock distribution Options for 2.5 V or 3.3 V power supply Low jitter clock trees Core current consumption of 122 mA Logic translation On-chip Low Drop Out (LDO) Regulator for superior Clock and data signal restoration power supply rejection Wired communications: OTN, SONET/SDH, GE, Performance 10 GE, FC and 10G FC Ultra low additive jitter of 38 fs RMS PCI Express generation 1/2/3 clock distribution Wireless communications High performance microprocessor clock distribution Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2016, Microsemi Corporation. All Rights Reserved.ZL40206 Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 Change Summary . 4 1.0 Package Description 5 2.0 Pin Description . 6 3.0 Functional Description 7 3.1 Clock Inputs . 7 3.2 Clock Outputs 12 3.3 Device Additive Jitter . 16 3.4 Power Supply 17 3.4.1 Sensitivity to power supply noise . 17 3.4.2 Power supply filtering 17 3.4.3 PCB layout considerations 17 4.0 AC and DC Electrical Characteristics . 18 5.0 Performance Characterization . 21 6.0 Typical Behavior 22 7.0 Package Characteristics 24 8.0 Mechanical Drawing . 25 2 Microsemi Corporation